16efac59af
Merge pull request #106 from riscv/thread_details
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Properly show XLEN for each thread.
2017-09-01 11:51:29 -07:00
ce740d02d6
Properly show XLEN for each thread.
2017-09-01 11:29:15 -07:00
48cda64282
Merge pull request #97 from riscv/keepalive
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Add some keep_alive()s for use with slow targets.
2017-08-30 12:14:23 -07:00
12aca4ab7e
Merge branch 'riscv' into keepalive
2017-08-30 12:09:51 -07:00
3c25b9a0c4
Merge pull request #105 from riscv/memread
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memory read is now completely stable even on intermittently slow targets
2017-08-29 17:33:51 -07:00
6721988ce3
Ensure read_memory() only reads each address once.
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Previously it might read an address multiple times if an abstract
command took longer to execute than expected.
The new implementations reads from the target how far it has gotten
along reading memory, and resumes from there if cmderr=busy.
This ended up being a bigger change than I envisioned, but in the end it
deleted more lines than it added, so I'm happy. :-)
2017-08-29 17:25:04 -07:00
94d7b05046
Merge pull request #104 from riscv/debug_newline
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Remove unnecessary \n
2017-08-29 10:40:52 -07:00
2efc415db4
Finally nailed memory read on slow targets
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The downloaded program now post-increments, and there's no longer an
attempt to read the current address from the target. This made it easier
to fix the problem where at the start of the loop the current address
was already read (in regular entry) or has not yet been read (when the
first round through the loop encountered busy more than once, or busy
was encountered at least once later on).
2017-08-28 11:17:55 -07:00
5f53655e65
Fix off-by-one error.
2017-08-26 18:25:10 -07:00
eef9442aa7
Remove redundant code.
2017-08-26 17:50:05 -07:00
5bdee8bc66
Fix off-by-3 error on 64-bit targets.
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This caused everything to fall apart when debugging slow 64-bit targets.
2017-08-26 17:49:13 -07:00
8bcec87cc1
Remove unnecessary \n
2017-08-26 16:53:00 -07:00
92ef328161
Don't reset DMI when an abstract command is busy.
2017-08-25 18:14:08 -07:00
a9bcc48064
Remove unnecessary newlines.
2017-08-25 18:14:08 -07:00
322669ca98
Merge pull request #95 from riscv/memread
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Fix block memory reads on slow targets.
2017-08-25 16:57:07 -07:00
4d0e88d887
Merge pull request #100 from riscv/riscv_timeout_commands
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riscv: Add commands for setting timeouts
2017-08-25 09:49:15 -07:00
35a0b519d9
Merge pull request #102 from gnu-mcu-eclipse/riscv-sockaddr
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server.c: fix clang warning
2017-08-25 09:37:59 -07:00
b42bc76e2e
server.c: fix clang warning
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/Users/ilg/Work/openocd/openocd.git/src/server/server.c:305:22: error:
incompatible pointer types passing 'struct sockaddr_in *' to
parameter of type 'struct sockaddr *'
[-Werror,-Wincompatible-pointer-types]
getsockname(c->fd, &addr_in, &addr_in_size);
^~~~~~~~
/usr/include/sys/socket.h:687:50: note: passing argument to parameter
here
int getsockname(int, struct sockaddr * __restrict, socklen_t *
__restrict)
2017-08-25 14:53:45 +03:00
94de39c221
riscv: Put commandd_handlers before they are needed. Tabs vs spaces.
2017-08-15 17:04:59 -07:00
879c274cb9
riscv: Add commands for setting timeouts
2017-08-15 15:59:40 -07:00
0ff4103a26
Reset address if target was busy during bust write
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Improve Issue #98 .
DebugCompareSections is still failing for me (with an instrumented
sometimes-slow spike), but MemTestBlock now passes reliably.
2017-08-15 15:47:35 -07:00
66806aa70d
Merge pull request #99 from riscv/cast
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Remove some unnecessary casts.
2017-08-15 14:55:44 -07:00
5c39079a62
Remove some unnecessary casts.
2017-08-15 14:29:24 -07:00
5092f96105
Add some keep_alive()s for use with slow targets.
2017-08-15 13:31:06 -07:00
0d74c8689d
Fix block memory reads on slow targets.
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The interesting new code concerns ignore_prev_addr and
this_is_last_read.
Additionally, I tweaked some debug output, and optimized
riscv_batch_run() when the batch is empty.
2017-08-14 15:02:19 -07:00
45f28081e1
Merge pull request #94 from riscv/memread
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Fix a corner case in block memory read.
2017-08-13 14:44:15 -07:00
2706df0ec3
Fix a corner case in block memory read.
2017-08-13 14:14:23 -07:00
1af0c09a85
Merge pull request #92 from riscv/FE_402_fix
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Fe 402 fix
2017-08-13 11:03:12 -07:00
3109da7dfd
Force actual read from prog buffer for the last transaction in read_memory()
2017-08-12 14:51:12 -07:00
e676d3dae6
Fixed off-by-one error in previous commit
2017-08-11 17:46:35 -07:00
96eb73c83e
Merge pull request #90 from riscv/FE_402_fix
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Fix reads beyond requested memory range
2017-08-10 18:13:13 -07:00
39b01259fa
fixed memory leak introduced by previous commit
2017-08-10 16:37:50 -07:00
b5692585de
Fix reads beyond requested memory range
2017-08-10 14:27:11 -07:00
b132fac804
Merge pull request #88 from riscv/read0
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Fix assertion failure when reading from address 0.
2017-08-09 16:26:19 -07:00
efcfcf555f
Fix assertion failure when reading from address 0.
2017-08-09 12:42:17 -07:00
97ea54030c
Merge pull request #87 from riscv/gdb_next_port
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When gdb_port is 0, don't increment it.
2017-08-08 10:01:26 -07:00
b897807224
When gdb_port is 0, don't increment it.
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Usually incrementing to get the next port is a good idea, but when set
to 0 the idea is to find an arbitrary unallocated port. 1 is almost
certainly not helpful.
2017-08-07 13:55:37 -07:00
b9822ab1b8
Merge pull request #86 from riscv/debug
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Display register numbers in a more usable format.
2017-07-27 14:49:29 -07:00
46b5f913c7
Display register numbers in a more usable format.
2017-07-27 13:45:26 -07:00
73dee3ad4a
Merge pull request #85 from riscv/print_port
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Print out which port OpenOCD is listening on.
2017-07-26 07:51:37 -07:00
753d15e22c
Print out which port OpenOCD is listening on.
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This is essential when a test environment asks OpenOCD to listen on port
0, so that the environment can easily discover which port is actually
being used.
2017-07-25 14:08:10 -07:00
79329f21a3
Merge pull request #84 from riscv/reset
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Fix infinite loop in reset.
2017-07-16 12:47:41 -07:00
b032eb1bcc
Use a wall clock timeout to complete reset.
2017-07-16 11:48:12 -07:00
f0f1df1061
Fix infinite loop in reset.
2017-07-14 12:50:11 -07:00
43c6fd3b8f
Merge pull request #83 from riscv/triggers
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Share trigger code between 0.11 and 0.13 code.
2017-07-13 18:04:34 -07:00
d60dbd60e8
Share trigger code between 0.11 and 0.13 code.
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The actual implementation of triggers didn't change between those two
versions, so there's no need to duplicate the code.
In the process, I also fixed a minor multicore bug where tselect didn't
always get written on all harts.
2017-07-12 19:54:40 -07:00
cc2c2e7a65
Merge pull request #82 from riscv/comment
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Forgot to commit this follow up to PR #79
2017-07-12 19:45:40 -07:00
2deb02695e
Forgot to commit this follow up to PR #79
2017-07-12 17:51:38 -07:00
46b91c9b0d
Merge pull request #79 from riscv/abstract_regs
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Use abstract command to access registers if possible
2017-07-12 17:50:46 -07:00
09bf86e31a
Keep around cmderr for callers to inspect.
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Use this to only change abstract register access behavior when cmderr
explicitly says the requested operation is unsupported.
2017-07-12 14:36:09 -07:00
Palmer Dabbelt
Tim Newsome
Liviu Ionescu
Megan Wachs
Gleb Gagarin
Gleb Gagarin