At gdb attach, the event TARGET_EVENT_GDB_ATTACH is in charge of
halting the target.
For HW thread, rtos_update_threads() should be called after the
event to detect and record the new 'halted' status. Instead it is
called immediately before the event, thus reading the status
before the halt.
Move after the event the call to rtos_update_threads().
Change-Id: Iab3480ea0f5283ed6580f0f6c11200083197d1e9
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5983
Tested-by: jenkins
Use a TAB in place of 4 spaces
Change-Id: Ic34b7c3ef24078d2c36a193d4dd079bca5a7ef2e
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: a4cdce0129 ("gdb_server: prevent false positive valgrind report")
Reviewed-on: http://openocd.zylin.com/5982
Tested-by: jenkins
Reviewed-by: Jonathan McDowell <noodles-openocd@earth.li>
The targets armv7a in file cortex_a.c inherit the register list
from file armv4_5.c thus, depending on the core status, some
register get marked as not existing.
For HW threads other than current target, the registers in the
list are not checked for existence and are all forwarded to GDB
that in turns complains for too many data:
Remote 'g' packet reply is too long (expected 68 bytes, got 104 bytes)
Check all the attributes of the registers and pass to GDB only the
valid registers.
To test it, use a SMP cortex-a target (2 cores are enough) and add
-rtos hwthread
to all the cores. Connect GDB to OpenOCD and issue the GDB command
info threads
Change-Id: Ie66119fe83a3c8d53e9d18dda39e60fd97769669
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5981
Tested-by: jenkins
only core0 is brought up by bootloader
Change-Id: I1d6b5e6ba7498beadbf3805f4271f0197e411bd5
Signed-off-by: Jiri Kastner <cz172638@gmail.com>
Reviewed-on: http://openocd.zylin.com/5980
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Reviewed-by: Jonathan McDowell <noodles-openocd@earth.li>
The target code for assert reset on cortex_a has been patched on
commit b0698501b0 ("cortex_a: fix cortex_a_assert_reset() if
srst_gates_jtag") then in cdba6ba0ad ("cortex_a: fix reset for
SWD transport") to workaround the mismatch between jtag and swd
implementations. See discussion for the second patch at
http://openocd.zylin.com/3641/
While all of these mismatches should hopefully be cleaned by the
reset framework rework, an extension of the workaround of the
second patch is required for dapdirect transports, either
dapdirect_swd and dapdirect_jtag.
Extend the existing workaround to all non-jtag transports.
Change-Id: Ia6a9d43bab524cbb3de4c37ce24c45f25187353d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5979
Tested-by: jenkins
If OpenOCD is reading trace data from the target, at exit it
should stop the adapter to gather data, but should left the target
still producing them.
Add a helper in armv7m_trace to disable the adapter's trace and
call it during OpenOCD teardown.
This also provides a workaround for an issue in the firmware of
ST-Link V3 till version V3J7. If the SWD connection is closed when
trace is active, at following connection the trace does not work
anymore.
Change-Id: I47ccab61405384938555096c5aca789eaa090d27
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5978
Reviewed-by: Jonathan McDowell <noodles-openocd@earth.li>
Tested-by: jenkins
This was flagged by lintian against the Debian package; the text stating
there are no invariant sections deviates from the official GNU wording.
Update it to match the text at the bottom of:
https://www.gnu.org/licenses/old-licenses/fdl-1.2.en.html
Change-Id: Ie222237a8eede24c1b71218b05e1513b74208a47
Signed-off-by: Jonathan McDowell <noodles@earth.li>
Reviewed-on: http://openocd.zylin.com/5974
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Automake issues a warning
Makefile.am:46: warning: wildcard $(srcdir: non-POSIX variable name
Makefile.am:46: (probably a GNU make extension)
because the GNU make function 'wildcard' is not POSIX.
Also the GNU make function 'shell' triggers a similar warning.
Use the POSIX extension '!=', that executes an arbitrary shell
command, to replace the GNU make 'wildcard'.
Don't include the file 'NEWS' because automake already includes it
by default.
Change-Id: Ice560c3789cec4f3f2197a255d6f5af7b1fde634
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5965
Tested-by: jenkins
Reviewed-by: Jonathan McDowell <noodles-openocd@earth.li>
The warning message regarding wrong verification checksum for LPC2000, claims that the verification will fail, but the checksum written correctly by openocd. Clarify this in the warning message.
Change-Id: I929ac767f7f9fdad9bace250c8c04a776462800a
Signed-off-by: Luca Lindhorst <l.lindhorst@wut.de>
Reviewed-on: http://openocd.zylin.com/5956
Tested-by: jenkins
Reviewed-by: Jonathan McDowell <noodles-openocd@earth.li>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Add `riscv info` command. Final output is "TCL format" and looks like this:
```
hart.xlen 64
hart.trigger_count 4
dm.abits 6
dm.progbufsize 2
dm.sbversion 0
dm.sbasize 0
dm.sbaccess128 0
dm.sbaccess64 0
dm.sbaccess32 0
dm.sbaccess16 0
dm.sbaccess8 0
```
* Add `riscv info` command.
This command displays some basic information that OpenOCD has detected
about the target. The output is displayed in YAML so it can easily be
parsed. Example of current output:
```
Hart:
XLEN: 32
trigger count: 4
Debug Module:
abits: 6
progbufsize: 2
sbversion: 0
sbasize: 0
sbaccess128: 0
sbaccess64: 0
sbaccess32: 0
sbaccess16: 0
sbaccess8: 0
```
Change-Id: If920c083ff6ec9f482c50f913cd8ceaa62461217
Signed-off-by: Tim Newsome <tim@sifive.com>
* Disable workflow inherited from upstream.
Change-Id: Ifc5ed1b4f5ec2278b8bcf3279c9fd462e469fefa
Signed-off-by: Tim Newsome <tim@sifive.com>
* Switch from YAML to TCL "set array" input format.
Change-Id: I3833210e5bf6d7cffc9934c04ec5201ae7732ad8
Signed-off-by: Tim Newsome <tim@sifive.com>
* Remove indent in `riscv info` output.
That was getting a little too cute, and probably more confusing than
helpful.
Change-Id: Ie51416f53ab4b69294962f0565767d370db82867
Signed-off-by: Tim Newsome <tim@sifive.com>
* Fix error handling in read_memory_progbuf_one().
Be sure to restore mstatus/s0 even if there is a failure during the
operation.
Fixes#559.
Change-Id: Ib86ca2c7455bad4a668f34703566060a782116db
Signed-off-by: Tim Newsome <tim@sifive.com>
* Style fix suggested in review.
Change-Id: I444112a9dffea483b7d0e5f96ef7bbdaf58d249f
Signed-off-by: Tim Newsome <tim@sifive.com>
This is a fix for an issue reported by Joe Stoy at:
https://sourceforge.net/p/openocd/mailman/message/37128537/
When clearing sbcs.sbbusyerror, preserve other bits in the sbcs
register that are needed for subsequent system bus transactions.
The git preliminarily version of clang 12.0.0_r370171
f067bc3c0ad6 reports an error in the expansion of the macro
SMI_READ_REG():
error: '(' and '{' tokens introducing statement expression
appear in different macro expansion contexts
[-Werror,-Wcompound-token-split-by-macro]
Remove one intermediate macro expansion to make clang happy.
Change-Id: I8ae6d9c18808467ba8044d70cbf0a4f76a18d3e6
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5958
Tested-by: jenkins
Reviewed-by: Xiaofan <xiaofanc@gmail.com>
This should provide greater compatibility with different OpenULINK
targets which might be using various endpoints numbers. Since they're
advertised in the USB descriptor anyway it makes sense to autodetect
them.
Interface is no longer claimed before attempting to load firmware to a
freshly booted device, so I have no idea if this will break on windows
or other uncommon systems (Paul).
Change-Id: Iee10dcb6911dcf46239c430e174d9f98b5bde3c2
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2445
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The 'historically' main repository of jimtcl in repo.or.cz has
lost sync with the github current main repository since July 2020.
The new tag 0.80 is not present in repo.or.cz.
The developer of jimtcl has been in contact with the admins of
repo.or.cz to fix the not better described sync issues and has now
decided to stop any further tentative. A new README has been added
on 2020-11-19 in the old repository to inform that it is abandoned
in favour of github. The old content in repo.or.cz will remain due
to forks that still exists in the same server.
Switch OpenOCD git submodules to fetch jimtcl code from the main
development repository in github.
Change-Id: Ia2d59f1347ccfe374538b38131badfd46054eb91
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5948
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
The use of 'void *' makes the pointer arithmetic incompatible with
standard C, even if this is allowed by GCC extensions.
The use of 'void *' can also hide incorrect pointer assignments.
Switch to 'uint8_t *' and add GCC warning flag to track any use of
pointer arithmetic extension.
Change-Id: Ic4d15a232834cd6b374330f70e2473a359b1607f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5937
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Commit 80f1a92bd7 ("mips64: Add generic mips64 target support")
adds a log of the target's program counter in function
mips_mips64_debug_entry() by directly casting the little-endian
buffer in pc->value.
This is going to print an incorrect value on big-endian hosts.
Use the function buf_get_u64() to return the register value.
Not tested on real HW. Issue identified with GCC compiler flag
'-Wcast-align=strict' after change http://openocd.zylin.com/5937/
("target/register: use an array of uint8_t for register's value").
Change-Id: Icbda2b54a03fdec287c804e623f5db4252f9cd2a
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 80f1a92bd7 ("mips64: Add generic mips64 target support")
Reviewed-on: http://openocd.zylin.com/5944
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
The original code passes to ->read_core_regs() and to
->read_xpsr() the pointer to the little-endian buffer reg.value.
This is incorrect because the two functions above require a
pointer to uint32_t, since they already run the conversion with
arm_le_to_h_u32() in the jtag callback.
This causes a mismatch on big-endian host and the registers get
read with the incorrect endianness.
Use an intermediate buffer to read the registers as uint32_t and
to track the destination reg.value pointer, then copy the value in
reg.value after the call to jtag_execute_queue().
Tested with qemu-armeb and an OpenOCD built through buildroot
configured for cortex-a7 big-endian.
Note that if jtag_execute_queue() fails, the openocd register
cache is not updated, so the already modified flags 'valid' and
'dirty' are incorrect. This part should be moved after the call to
jtag_execute_queue() too.
Change-Id: Iba70d964ffbb74bf0860bfd9d299f218e3bc65bf
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5943
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Commit fc2abe63fd ("armv7m: use generic arm::core_mode") adds
two special modes for ARMv6M and ARMv7M in struct arm_mode_data[].
While these modes do not have any additional register to be dumped
by command 'arm reg', the command still prints an header for these
modes but not followed by any register.
Detect the special modes for ARMv6M and ARMv7M and skip them to
avoid printing the useless header.
Change-Id: I04145769e5742624f143c910eebf9a6f6d8e3cdc
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: fc2abe63fd ("armv7m: use generic arm::core_mode")
Reviewed-on: http://openocd.zylin.com/5942
Tested-by: jenkins
Commit fed7131049 ("armv4_5: support weirdo ARMv6 secure monitor
mode") introduces the secure mode 28 of ARMv6 as a synonymous of
mode 22 (MON), but does not add it in the switch/case in command
'arm reg'.
When command 'arm reg' scans the array arm_mode_data[] on targets
without secure modes, it does not detect the new secure mode as
not supported by the architecture, thus triggers a segmentation
fault when it try to read the register's value from unallocated
memory.
Issue detected with target arm926ejs.
Add the new mode in the switch/case and treat it as the mode MON.
Change-Id: I2b72cc558e097879a7ee6ea601200bfda6b60270
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: fed7131049 ("armv4_5: support weirdo ARMv6 secure monitor mode")
Reviewed-on: http://openocd.zylin.com/5941
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
From JEP106AZ, released on May 24, 2019.
Change-Id: I768b7077ec6abcd19ae1530b5715c7ea993add67
Signed-off-by: Boran Car <boran.car@hex-five.com>
Reviewed-on: http://openocd.zylin.com/5244
Tested-by: jenkins
Reviewed-by: Jonathan McDowell <noodles-openocd@earth.li>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Jiri Kastner <cz172638@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Real Time Transfer (RTT) is an interface specified by SEGGER based on
basic memory reads and writes to transfer data bidirectionally between
target and host.
Every target that supports so called "background memory access", which
means that the target memory can be accessed by the debugger while the
target is running, can be used.
RTT is especially of interest for targets which do not support Serial
Wire Output (SWO) (e.g. ARM Cortex-M0) or where using semihosting is
not possible (e.g. real-time applications) [1].
The data transfer is organized in channels where each channel consists
of an up- and/or down-channel. See [2] for more details.
Channels are exposed via TCP connections. One or more RTT server can be
assigned to each channel to make them accessible to an unlimited number
of TCP connections.
The current implementation does not respect buffer flags which are used
to determine what happens when writing to a full buffer.
Note that the implementation is designed in a way that the RTT
operations can be directly performed by an adapter (e.g. J-Link).
[1] https://devzone.nordicsemi.com/tutorials/6/
[2] https://www.segger.com/jlink-rtt.html
Change-Id: I8bc8a1b381fb74e08b8752d5cf53804cc573c1e0
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/4055
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reading of DPIDR is the very first operation after JTAG to SWD sequence.
Without this change if DPIDR read fails then swd connect fails.
Keep trying JTAG to SWD sequence and DPIDR read until success
or timeout 0.5 sec. It makes setting of adapter srst delay on SWD transport
mostly unnecessary.
Also test for ERROR_WAIT (which should not occur according to
IHI 0031E B4.3.2 but a quirk is known) and if bus is kept stalled
then issue abort to make the next connect possible.
Change-Id: Id8fe6618605bbeb4fed5061e987ed55de90a35f2
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5730
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
If dap_dp_read_atomic() in 30 trials loop fails, dap->do_reconnect is set.
Following dap_dp_read_atomic() calls dap_queue_dp_read() which in case
of SWD transport calls swd_queue_dp_read(). It starts
with swd_check_reconnect() and it calls swd_connect() because
dap->do_reconnect is set. swd_connect() does some initialization,
reads DPIDR and calls dap_dp_init() again!
Moreover if dap_dp_init() is called from cortex_m_reset_(de)assert()
one level of recursion is necessary to reconnect the target.
Introduce dap_dp_init_or_reconnect() for use in cortex_m reset
and similar.
Remove loop of 30 atomic reads of DP_STAT to prevent unwanted recursion.
Change-Id: I54052fdefe50bf5f7c7b59fe751fe2063d5710c9
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5729
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
- rename and cleanup to arm-usb-ocd-h-cjtag file to be consistent
- add copy of olimex-arm-jtag-cjtag.cfg as arm-usb-tiny-h-cjtag.cfg
- did not remove olimex-arm-jtag-cjtag.cfg (should be deprecated)
Every debug log of OpenOCD contains approximately 130 lines like:
Debug: 264 147 command.c:354 register_command_handler(): registering 'flash'...
Because only root name of the command is logged, most of lines is not
too informative. E.g. registering 'flash' is repeated 14 times.
Karl Passon submitted the patch [1] changing the logged cmd name from
root to lowest level. It makes the log better. Unfortunately we also have
'reset_config' and 'cortex_m reset_config' and similar which looks
equal in the log after [1].
Moreover [1] has not been reviewed for 5 years.
So my guess is that nobody uses that crap in debug log.
Save more than 10 kbytes in any debug log and make log analyse easier
by blocking log command in #if 0 block.
If some developer eventually needs to debug cmd registering he can easily
enable logging again.
[1] http://openocd.zylin.com/2765
Change-Id: Ib7e528aadd692fd0da2e3c005b4c5a484551b728
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5928
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Christopher Head <chead@zaber.com>
STM32L5 have 512 Kbytes of Flash memory with dual bank architecture.
STM32L5 flash is quite similar to L4 flash, mainly register names
and offsets and some bits are changed.
NON-SECURE flash is located at 0x8000000 like L4 devices, so no
big change is needed (secure flash will be subject of another change).
Note: flash driver name is set stm32l5x, in order to extend the commands
with specific L5 commands (to manage TZEN for example ...)
Note: this works only when TZEN=0
Change-Id: Ie758abb4aa19a3f29eeb0702d7dcb43992e4c639
Signed-off-by: Michael Jung <mijung@gmx.net>
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5510
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This change is a preparation for STM32L5 support on top of L4 driver
STM32L5 flash is quite similar to L4 flash, mainly register names
and offsets and some bits are changed.
flash_regs table is introduced within stm32l4_flash_bank struct in order
to get correct register offsets, by using the driver internal function
'stm32l4_get_flash_reg_by_index'.
To use efficiently register indexes, stm32l4 _[get|read|write]_flash_reg
functions are surcharged to accept register indexes.
IMPORTANT: stm32l4_write_option is not surcharged, and they always accept
the option register offset.
tested on NUCLEO-G474RE and STM32L4R9I-DISCO
Change-Id: I739d3e97d63b831af6aa569c5629db0000209551
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5509
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Avoid multiple definition of cmsis_dap_usb_backend and
cmsis_dap_hid_backend using 'extern'.
Move the prototypes in cmsis_dap.h.
Remove the useless #if/#endif around the prototypes.
Change-Id: I8d73fe148e2155620244bc887d4235e9af530e30
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5790
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
http://openocd.zylin.com/4831 has following problems in selecting
USB device/interface to connect:
- attempts connection to any device with user class and 2 bulk endpoints
- regardless of cmsis_dap_vid_pid or cmsis_dap_serial setting
connects to the first suitable device
Distinguish between real match and no filtering cases and use that info
appropriately.
Add debug messages to show why the interface is refused.
Move CMSIS-DAP interface string detection before checking of class/endpoints
to give more understandable debug log in the case the device is refused.
Keep track of reliable matches in both device and interface enumeration.
First search for the interface with CMSIS-DAP in the interface string.
If it fails, chose the first suitable interface.
Change-Id: Ia1aacd5631a9f5c5db580bfb5745ceb6240d61ad
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5789
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
This change implements CMSIS-DAP v2 which works with raw USB bulk transfers.
The old driver is now split into a generic CMSIS part and a HID backend,
with a new raw USB backend for CMSIS-DAP v2.
New commands:
- cmsis_dap_backend (usb_bulk | hid | auto)
- cmsis_dap_usb interface <interface number>
Change-Id: I4218477b12ccbfe19c9b332321cd21394bf44e30
Signed-off-by: Mickaël Thomas <mickael9@gmail.com>
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4831
Tested-by: jenkins
Change-Id: I4fea29f07f4d3b8b2578b538ef0eef5f1eea285f
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5876
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
PSoC6 erases flash to 0x00 not more common 0xff, so a device
with erased flash loads xPSR.T=0 from the zeroed reset vector.
Wrong thumb bit value caused a target algorithm failed with HardFault.
The low level write to xPSR solved the problem only if xPSR cached
copy was not marked dirty.
Later commit 49bd64347a fixed T setting
for all Cortex-M target algorithms.
Since 49bd64 this part of code is useless as xPSR target_start_algorithm()
sets always xPSR dirty so the effect of the low level write is eliminated
(and proper setting of thumb bit is ensured in target_start_algorithm())
Change-Id: I68aea5e921fbc6203f2fe91a45f10d22869327de
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5875
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
If a Cortex-M (not M0, M0+) target was stopped in the middle of
a conditional IT block or in the load/store multiple instruction,
cortex_m_debug_entry() used wrong xPSR bits to detect it and then
cleared 8 bits of the exception number from xPSR
- probably wrong bit mask again.
I believe clearing of the ICI/IT bits in cortex_m_debug_entry() has no
reason as Cortex-M does not use instruction injecting.
Remove the wrong code.
The change was originally a part of http://openocd.zylin.com/4862
It is now re-submitted as #4862 is not ready.
Change-Id: If91cd91d1b81b2684f7d5f10cf20452cde1a7f56
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5874
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Register xPSR is indexed directly with its value 16 or with the
incorrect enum ARMV7M_xPSR.
Replace them with the new enum ARMV7M_REGSEL_xPSR.
Change-Id: I86600e7f78e39002ce45f66d4792d5067c1f541b
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5873
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Old stlink firmware in stlink V1 and stlink V2 pre-J15 do not
handle FPU registers in the read_reg() and write_reg() API.
Add code to be compatible with the new API of OpenOCD.
Change-Id: Ib0439c5294b6911ea75efe8c7fa085b014317a4b
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5883
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
The API of hla have been defined from ST-Link basic operations.
By chance, all the current implementation of hla (st-link, ti-icdi
and nulink) share the same way to handle the parameter 'num' of
the API read_reg() and write_reg(), that is simply using it to
initialize the field REGSEL (bits [6:0]) of armv7m Debug Core
Register Selector Register (DCRSR).
Add a comment in the API definition to highlight this, in case it
get used by a further hla implementation, then rename as 'regsel'
the 'num' parameter.
Change-Id: I4b6a2c7d78b4fc4de2b9b2bdba065414b15c6ba3
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5882
Reviewed-by: Edward Fewell <edwardfewell@hotmail.com>
Tested-by: jenkins
Reviewed-by: Zale Yu
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Consolidate low level register read/write.
Floating point registers were handled by target_read/write_u32
unlike other registers handled by cortexm_dap_read/write_coreregister_u32
There is no reason to do so in cortex_m.
Remove cortexm_dap_read/write_coreregister_u32
and use cortex_m_load/store_core_reg_u32 directly.
Similarly HLA adapters register read/write interface supports all registers
so use it for any floating point and other registers.
Change-Id: Ida679e5f4fec02d94ffb0bd3f265ed7ed2221cdc
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5864
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Move primask/basepri/faultmask/control packing/unpacking from
cortex_m.c and hla_target.c to armv7m.c armv7m_read_core_reg()
and armv7m_write_core_reg() where also the FP 32/64-bit registers
conversion takes place.
Introduce a new hidden register ARMV7M_PMSK_BPRI_FLTMSK_CTRL
for packing/unpacking of special registers in the register cache.
The new packing/unpacking is endianess safe.
While on it improve returned error codes and LOG_ messages.
Just minimal changes in cortex_m.c and hla_target.c, will be
consolidated in the next patch.
Change-Id: Id51e764e243e54b5fdaadf2a202eee7c4bc729fe
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5863
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tim Newsome
Antonio Borneo
Jiri Kastner
Jonathan McDowell
Luca Lindhorst
Jan Matyas
Paul Fertser
Łukasz Misek
Tarek BOCHKATI
Boran Car
Marc Schink
Tomas Vanek
Kevin Mills
Tarek BOCHKATI
Mickaël Thomas