ethernet/rtl
Sean Anderson 3b836d3ad0 nrzi_decode: Add reset input
Most other modules in the recieve path are reset when signal_status goes
low. This one didn't, and it was difficult to test because of this. In
particular, we need to ensure that this module behaves correctly when
switching between different bitstreams (such as for loopback).

While implementing this, I found some bugs in the way that nrzi_valid
was handled: it wasn't saved from when the transfer actually happened,
and the data wasn't qualified properly.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2022-11-30 18:14:23 -05:00
..
axis_replay_buffer.v Add AXI stream replay buffer 2022-11-30 18:14:23 -05:00
common.vh Automatically dump signals 2022-10-30 14:20:48 -04:00
descramble.v descramble: Pass through scrambled_valid 2022-11-05 11:54:39 -04:00
io.vh Add pmd 2022-08-06 14:02:44 -04:00
iverilog_dump.v Automatically dump signals 2022-10-30 14:20:48 -04:00
mdio.v Automatically dump signals 2022-10-30 14:20:48 -04:00
mdio_io.v Automatically dump signals 2022-10-30 14:20:48 -04:00
mdio_regs.v pcs: Add false_carrier signal 2022-11-05 12:37:18 -04:00
mii_io_rx.v Automatically dump signals 2022-10-30 14:20:48 -04:00
mii_io_tx.v Automatically dump signals 2022-10-30 14:20:48 -04:00
nrzi_decode.v nrzi_decode: Add reset input 2022-11-30 18:14:23 -05:00
nrzi_encode.v Automatically dump signals 2022-10-30 14:20:48 -04:00
pcs.vh pcs: Split into rx/tx 2022-10-30 21:32:02 -04:00
pcs_rx.v pcs: Add false_carrier signal 2022-11-05 12:37:18 -04:00
pcs_tx.v pcs: Split into rx/tx 2022-10-30 21:32:02 -04:00
phy_core.v Add phy_core 2022-11-05 12:37:18 -04:00
pmd_dp83223_rx.v pmd_dp83223: Delay signal_status by an additional clock 2022-10-30 22:02:32 -04:00
scramble.v scrambler: Fix wrone assignment type 2022-11-02 00:16:43 -04:00