Sean Anderson 897326dbdb Move default_nettype/timescale declaration to common.vh ... We will need this in every verilog file, so consolidate things a bit. In terms of timescale, we need to modify the post-synthesis verilog generation a bit in order to avoid the module's timecale being inadverdently overwritten. Signed-off-by: Sean Anderson <seanga2@gmail.com>		2022-08-24 12:04:10 -04:00
..
common.vh	Move default_nettype/timescale declaration to common.vh	2022-08-24 12:04:10 -04:00
io.vh	Add pmd	2022-08-06 14:02:44 -04:00
pcs.v	Move default_nettype/timescale declaration to common.vh	2022-08-24 12:04:10 -04:00
pmd.v	common: Add levels parameter to DUMP	2022-08-06 21:47:21 -04:00