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ethernet
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WIP 100BASE-TX PHY
29 Commits 2 Branches 0 Tags 290 KiB
Verilog 50.1%
Python 46.8%
Makefile 2.3%
SystemVerilog 0.8%
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Sean Anderson 799aeb92d6 Ignore post-synthesis verilog 
These files are build artifacts. Ignore them.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
 		2022-08-21 12:36:36 -04:00
rtl pcs: rx: Only flush on state change 2022-08-06 22:08:09 -04:00
tb Make testbenches a module 2022-08-21 12:36:28 -04:00
.gitignore Ignore post-synthesis verilog 2022-08-21 12:36:36 -04:00
4b5b.gtkw Initial commit 2022-05-23 20:57:03 -04:00
Makefile Add post-synthesis simulation support 2022-08-06 21:47:21 -04:00