67 lines
1.5 KiB
Makefile
67 lines
1.5 KiB
Makefile
# SPDX-License-Identifier: AGPL-3.0-Only
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# Copyright (C) 2022 Sean Anderson <seanga2@gmail.com>
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Q = 1
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SYNTH = yosys
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PNR = nextpnr-ice40
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ICARUS = iverilog
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VVP = vvp
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.PHONY: all
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all: rtl/pcs.asc
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.PHONY: FORCE
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FORCE:
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%.json: %.v
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$(SYNTH) -q -E $@.d -p "synth_ice40 -top $(*F)" -b json -o $@ -f verilog $<
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%.post.v: %.json %.v
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( grep timescale $*.v && echo '`include "common.vh"' && \
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$(SYNTH) -q -b verilog -f json $< ) | sed 's/endmodule/`DUMP(1)\n\0/g' > $@
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IFLAGS := -g2012 -Wall
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define run-icarus =
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$(ICARUS) $(IFLAGS) -I$(<D) -M$@.pre -s $(TOP) -o $@ $< $(EXTRA_V) && \
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( echo -n "$@: " && tr '\n' ' ' ) < $@.pre > $@.d; RET=$$?; rm -f $@.pre; exit $$RET
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endef
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%.vvp: TOP = $(*F)
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%.vvp: %.v
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$(run-icarus)
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%.post.vvp: TOP = $(*F)
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%.post.vvp: EXTRA_V := $(shell $(SYNTH)-config --datdir)/ice40/cells_sim.v
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# Don't warn about unused SB_IO ports
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%.post.vvp: IFLAGS += -Wno-portbind
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%.post.vvp: %.post.v
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$(run-icarus)
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%.asc: %.json
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$(PNR) --pcf-allow-unconstrained --freq 125 --hx8k --package ct256 --json $< --asc $@
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-include $(wildcard rtl/*.d)
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export LIBPYTHON_LOC := $(shell cocotb-config --libpython)
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VVPFLAGS := -M $(shell cocotb-config --lib-dir)
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VVPFLAGS += -m $(shell cocotb-config --lib-name vpi icarus)
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define run-vvp =
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MODULE=tb.$* $(VVP) $(VVPFLAGS) $< -fst +vcd=$@
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endef
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%.fst: rtl/%.vvp tb/%.py FORCE
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$(run-vvp)
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%.post.fst: rtl/%.post.vvp tb/%.py FORCE
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$(run-vvp)
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.PHONY: test
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test: $(addsuffix .fst,pcs pmd) $(addsuffix .post.fst,pcs pmd)
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.PHONY: clean
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clean:
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rm *.fst
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cd rtl && rm -f *.json *.asc *.pre *.vvp *.d *.post.v
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