ethernet/rtl
Sean Anderson 494ef2a2a9 pcs: Split into rx/tx
For easier integration, split the PCS into its rx and tx components.
This was already done on the module level, but now they live in separate
files.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2022-10-30 21:32:02 -04:00
..
common.vh Automatically dump signals 2022-10-30 14:20:48 -04:00
descramble.v descramble: Determine relock_next from idle_counter directly 2022-10-30 20:53:18 -04:00
io.vh Add pmd 2022-08-06 14:02:44 -04:00
iverilog_dump.v Automatically dump signals 2022-10-30 14:20:48 -04:00
mdio.v Automatically dump signals 2022-10-30 14:20:48 -04:00
mdio_io.v Automatically dump signals 2022-10-30 14:20:48 -04:00
mdio_regs.v Automatically dump signals 2022-10-30 14:20:48 -04:00
mii_io_rx.v Automatically dump signals 2022-10-30 14:20:48 -04:00
mii_io_tx.v Automatically dump signals 2022-10-30 14:20:48 -04:00
nrzi_decode.v Automatically dump signals 2022-10-30 14:20:48 -04:00
nrzi_encode.v Automatically dump signals 2022-10-30 14:20:48 -04:00
pcs.vh pcs: Split into rx/tx 2022-10-30 21:32:02 -04:00
pcs_rx.v pcs: Split into rx/tx 2022-10-30 21:32:02 -04:00
pcs_tx.v pcs: Split into rx/tx 2022-10-30 21:32:02 -04:00
pmd_io.v pmd_io: Calculate wraparound based on state and not state_next 2022-10-30 20:58:18 -04:00
scramble.v Automatically dump signals 2022-10-30 14:20:48 -04:00