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WIP 100BASE-TX PHY
71 Commits 2 Branches 0 Tags 285 KiB
Verilog 50.1%
Python 46.8%
Makefile 2.3%
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Sean Anderson 494ef2a2a9 pcs: Split into rx/tx 
For easier integration, split the PCS into its rx and tx components.
This was already done on the module level, but now they live in separate
files.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
 		2022-10-30 21:32:02 -04:00
rtl pcs: Split into rx/tx 2022-10-30 21:32:02 -04:00
tb pcs: Split into rx/tx 2022-10-30 21:32:02 -04:00
.gitignore Ignore post-synthesis verilog 2022-08-21 12:36:36 -04:00
4b5b.gtkw Initial commit 2022-05-23 20:57:03 -04:00
Makefile Automatically dump signals 2022-10-30 14:20:48 -04:00