12a4678442
This adds support for (de)scrambling as described in X3.263. The scrambler is fairly straightforward. Because we only have to recognize idles, and because the timing constraints are more relaxed (than e.g. the PCS), we can make several simplifications not found in other designs (e.g. X3.263 Annex G or DP83222). First, we can reuse the same register for the lfsr as for the input ciphertext. This is because we only need to record the scrambled data when we are unlocked, and we can easily recover the unscrambled data just by an inversion (as opposed to needing to align with /H/ etc). Second, it is not critical what the exact thresholds are for locking an unlocking, as long as certain minimums are met. This allows us to ignore edge cases, such as if we have data=10 and valid=2. Without these relaxed constraints, we would need to special-case this input to ensure we didn't miss the last necessary consecutive idle. But instead we just set the threshold such that one missed bit does not matter. To support easier testing, a test input may be used to cause the descramble to become unlocked after only 5us, instead of the mandated 361. This makes simulation go much faster. Signed-off-by: Sean Anderson <seanga2@gmail.com> |
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| .. | ||
| common.vh | ||
| descramble.v | ||
| io.vh | ||
| nrzi_decode.v | ||
| nrzi_encode.v | ||
| pcs.v | ||
| pmd.v | ||
| scramble.v | ||