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ethernet
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WIP 100BASE-TX PHY
41 Commits 2 Branches 0 Tags 290 KiB
Verilog 50.1%
Python 46.8%
Makefile 2.3%
SystemVerilog 0.8%
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Sean Anderson 4646500973 tb: Refactor out ClockEnable 
Several interfaces have ce signals. Create a common function for driving
these signals, similar to the Clock function.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
 		2022-08-27 13:09:30 -04:00
rtl Add (de)scrambling support 2022-08-27 13:06:38 -04:00
tb tb: Refactor out ClockEnable 2022-08-27 13:09:30 -04:00
.gitignore Ignore post-synthesis verilog 2022-08-21 12:36:36 -04:00
4b5b.gtkw Initial commit 2022-05-23 20:57:03 -04:00
Makefile Add (de)scrambling support 2022-08-27 13:06:38 -04:00