..
axis_mii_tx.v
axis_mii_tx: Add support for half duplex
2023-01-14 00:08:38 -05:00
axis_replay_buffer.v
Use separate process for non-resetting registers
2023-01-13 23:13:12 -05:00
axis_wb_bridge.v
Add AXIS-Wishbone bridge
2023-03-01 20:14:22 -05:00
common.vh
Automatically dump signals
2022-10-30 14:20:48 -04:00
descramble.v
descramble: Pass through scrambled_valid
2022-11-05 11:54:39 -04:00
hub.v
Add hub
2023-02-20 23:34:10 -05:00
hub_core.v
hub/phy_core: Export some status signals
2023-02-20 23:34:10 -05:00
io.vh
Add pmd
2022-08-06 14:02:44 -04:00
iverilog_dump.v
Automatically dump signals
2022-10-30 14:20:48 -04:00
led_blinker.v
Add LED blinker
2023-02-18 22:48:36 -05:00
mdio.v
Automatically dump signals
2022-10-30 14:20:48 -04:00
mdio_io.v
Automatically dump signals
2022-10-30 14:20:48 -04:00
mdio_regs.v
pcs: Add false_carrier signal
2022-11-05 12:37:18 -04:00
mii_elastic_buffer.v
mii_elastic_buffer: Don't use memory access hack on valid/err
2023-02-18 22:48:36 -05:00
mii_io_rx.v
Automatically dump signals
2022-10-30 14:20:48 -04:00
mii_io_tx.v
Automatically dump signals
2022-10-30 14:20:48 -04:00
nrzi_decode.v
nrzi_decode: Add reset input
2022-11-30 18:14:23 -05:00
nrzi_encode.v
Automatically dump signals
2022-10-30 14:20:48 -04:00
pcs.vh
pcs: Split into rx/tx
2022-10-30 21:32:02 -04:00
pcs_rx.v
pcs: Add false_carrier signal
2022-11-05 12:37:18 -04:00
pcs_tx.v
pcs: Split into rx/tx
2022-10-30 21:32:02 -04:00
phy_core.v
hub/phy_core: Export some status signals
2023-02-20 23:34:10 -05:00
phy_internal.v
Add examples
2023-02-20 23:34:10 -05:00
pmd_dp83223.v
Add DP83223-based PMD
2022-11-30 18:14:23 -05:00
pmd_dp83223_rx.v
pmd_dp83223_rx: Don't use SB_IO for signal_detect
2023-02-20 18:39:58 -05:00
scramble.v
scramble: Fix initial lfsr value
2023-01-09 20:51:59 -05:00
uart_rx.v
Add UART receive module
2023-02-28 23:50:36 -05:00
uart_tx.v
Add UART transmit module
2023-02-28 22:26:05 -05:00
wb_mux.v
Add wishbone mux
2023-02-18 22:48:36 -05:00