61 lines
1.3 KiB
Verilog
61 lines
1.3 KiB
Verilog
// SPDX-License-Identifier: AGPL-3.0-Only
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/*
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* Copyright (C) 2023 Sean Anderson <seanga2@gmail.com>
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*
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* A wishbone mux with extremely-simple address decoding.
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*/
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`include "common.vh"
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module wb_mux (
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/* Wishbone master */
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output reg m_ack, m_err,
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input m_cyc, m_stb, m_we,
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input [ADDR_WIDTH + SLAVES - 1:0] m_addr,
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input [DATA_WIDTH - 1:0] m_data_write,
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output reg [DATA_WIDTH - 1:0] m_data_read,
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input [SLAVES - 1:0] s_ack, s_err,
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output reg [SLAVES - 1:0] s_cyc, s_stb, s_we,
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output reg [ADDR_WIDTH * SLAVES - 1:0] s_addr,
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output reg [DATA_WIDTH * SLAVES - 1:0] s_data_write,
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input [DATA_WIDTH * SLAVES - 1:0] s_data_read
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);
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parameter ADDR_WIDTH = 5;
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parameter DATA_WIDTH = 16;
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parameter SLAVES = 4;
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integer i;
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reg selected;
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always @(*) begin
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s_cyc = {SLAVES{m_cyc}};
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s_stb = {SLAVES{1'b0}};
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s_we = {SLAVES{m_we}};
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s_addr = {SLAVES{m_addr[ADDR_WIDTH - 1:0]}};
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s_data_write = {SLAVES{m_data_write}};
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m_ack = 0;
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m_err = 0;
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m_data_read = {DATA_WIDTH{1'bX}};
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selected = 0;
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for (i = 0; i < SLAVES; i = i + 1) begin
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if (m_addr[ADDR_WIDTH + i] && !selected) begin
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m_ack = s_ack[i];
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m_err = s_err[i];
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m_data_read = s_data_read[i * DATA_WIDTH +: DATA_WIDTH];
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s_stb[i] = m_stb;
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s_we[i] = m_we;
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selected = 1;
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end
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end
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if (m_cyc && m_stb && !selected) begin
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m_ack = 0;
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m_err = 1;
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end
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end
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endmodule
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