This module implements the MII management interface ("MDIO"), and
translates frames into classic wishbone reads/writes. We use a
"state_counter" to keep track of how many additional bits we expect to
recieve before continuing on to the next field in the frame. We require
a preamble because it prevents ambiguity, and omitting it doesn't seem
to be very popular (seeing as it was removed for c45). Generally, even
if we find an error in the frame, we still procede through the states as
usual. This prevents any spurious reads/writes caused by misinterpreting
an unaligned data stream.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
This adds support for (de)scrambling as described in X3.263. The
scrambler is fairly straightforward. Because we only have to recognize
idles, and because the timing constraints are more relaxed (than e.g.
the PCS), we can make several simplifications not found in other
designs (e.g. X3.263 Annex G or DP83222).
First, we can reuse the same register for the lfsr as for the input
ciphertext. This is because we only need to record the scrambled data
when we are unlocked, and we can easily recover the unscrambled data
just by an inversion (as opposed to needing to align with /H/ etc).
Second, it is not critical what the exact thresholds are for locking an
unlocking, as long as certain minimums are met. This allows us to ignore
edge cases, such as if we have data=10 and valid=2. Without these
relaxed constraints, we would need to special-case this input to ensure
we didn't miss the last necessary consecutive idle. But instead we just
set the threshold such that one missed bit does not matter.
To support easier testing, a test input may be used to cause the
descramble to become unlocked after only 5us, instead of the mandated
361. This makes simulation go much faster.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Using -O allows grouping job output, which is helpful when output would
otherwise be interleaved (such as when running tests). However, it also
means that there is no tty attached to the job, resulting in cocotb
automatically turning off color. Detect whether we have a tty during the
parsing phase, and force color output if we do. Technically this should
probably take into account the existing value of COCOTB_ANSI_OUTPUT, but
I don't use it normally.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
We will need this in every verilog file, so consolidate things a bit. In
terms of timescale, we need to modify the post-synthesis verilog
generation a bit in order to avoid the module's timecale being
inadverdently overwritten.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
This adds support for running testbenches post-synethesis. Simulating
this way should (hopefully) catch most synthesis/simulation mismatches.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Sean Anderson