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.gitignore
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Added first help messages for cell types
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2015-10-14 16:27:42 +02:00 |
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Makefile.inc
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techlibs: Add `cmp2softlogic.v` to common
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2023-11-13 10:42:12 +01:00 |
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abc9_map.v
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techmap: Add support for [] wildcards in techmap_celltype.
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2020-08-02 22:46:48 +02:00 |
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abc9_model.v
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abc9: fix SCC issues (#2694)
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2021-03-29 22:01:57 -07:00 |
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abc9_unmap.v
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abc9: fix SCC issues (#2694)
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2021-03-29 22:01:57 -07:00 |
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adff2dff.v
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Fix syntax error in adff2dff.v
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2021-02-24 01:07:34 +01:00 |
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cellhelp.py
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Progress on cell help messages
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2015-10-17 02:35:19 +02:00 |
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cells.lib
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Added cells.lib
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2015-01-16 15:50:42 +01:00 |
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cmp2lcu.v
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verilog: significant block scoping improvements
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2021-01-31 09:42:09 -05:00 |
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cmp2lut.v
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verilog: significant block scoping improvements
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2021-01-31 09:42:09 -05:00 |
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cmp2softlogic.v
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techlibs: Add `cmp2softlogic.v` to common
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2023-11-13 10:42:12 +01:00 |
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dff2ff.v
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Add force_downto and force_upto wire attributes.
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2020-05-19 01:42:40 +02:00 |
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gate2lut.v
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Fix invalid verilog syntax
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2020-03-14 14:33:44 +01:00 |
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gen_fine_ffs.py
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Add $aldff and $aldffe: flip-flops with async load.
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2021-10-02 18:12:52 +02:00 |
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mul2dsp.v
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Fix files with CRLF line endings
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2021-06-09 12:16:33 +02:00 |
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pmux2mux.v
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Added techlibs/common/pmux2mux.v
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2014-01-17 20:06:15 +01:00 |
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prep.cc
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Run `future` as part of `prep`
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2023-09-13 11:32:36 +02:00 |
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simcells.v
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Add $aldff and $aldffe: flip-flops with async load.
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2021-10-02 18:12:52 +02:00 |
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simlib.v
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Add new `$check` cell to represent assertions with a message.
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2024-02-01 20:10:39 +01:00 |
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smtmap.v
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Add smtmap.v describing the smt2 backend's behavior for undef bits
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2022-10-20 15:48:18 +02:00 |
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synth.cc
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mult -> booth in synth.cc, to turn on use synth -booth
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2023-09-08 16:44:59 -07:00 |
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techmap.v
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Add bitwise `$bweqx` and `$bwmux` cells
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2022-11-30 18:24:35 +01:00 |
c7bf0e3b8f