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Jim Lawson fc1c9aa11f Update cells supported for verilog to FIRRTL conversion. 
Issue warning messages for missing parameterized modules and attempts to set initial values.
Replace simple "if (cell-type)" with "else if" chain.
Fix FIRRTL shift handling.
Add support for parameterized modules, $shift, $shiftx.
Handle default output file.
Deal with no top module.
Automatically run pmuxtree pass.
Allow EXTRA_FLAGS and SEED parameters to be set in the environment for tests/tools/autotest.mk.
Support FIRRTL regression testing in tests/tools/autotest.sh
Add xfirrtl files to test directories to exclude files from FIRRTL regression tests that are known to fail.
 		2019-02-15 11:14:17 -08:00
..
asicworld Update cells supported for verilog to FIRRTL conversion. 2019-02-15 11:14:17 -08:00
bram Added support for (single-clock) transparent memories to bram tests 2016-11-01 10:03:13 +01:00
errors Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique, 2018-10-25 02:37:56 +03:00
fsm Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests. 2016-09-22 11:49:29 -06:00
hana Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests. 2016-09-22 11:49:29 -06:00
lut cmp2lut: new techmap pass. 2019-01-02 07:53:31 +00:00
memories Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests. 2016-09-22 11:49:29 -06:00
opt opt_expr: improve simplification of comparisons with large constants. 2019-01-02 15:45:28 +00:00
realmath Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests. 2016-09-22 11:49:29 -06:00
sat Allow $size and $bits in verilog mode, actually check test case 2017-09-29 11:56:43 +02:00
share Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests. 2016-09-22 11:49:29 -06:00
simple Update cells supported for verilog to FIRRTL conversion. 2019-02-15 11:14:17 -08:00
smv Progress in SMV back-end 2015-06-19 14:08:46 +02:00
sva Squelch a little more trailing whitespace 2018-12-29 12:46:54 +01:00
svinterfaces Add missing .gitignore 2018-12-06 07:29:37 +01:00
techmap Added read-enable to memory model 2015-09-25 12:23:11 +02:00
tools Update cells supported for verilog to FIRRTL conversion. 2019-02-15 11:14:17 -08:00
unit Build hotfix in tests/unit/Makefile 2016-12-11 10:58:49 +01:00
various Modified errors into warnings 2018-06-05 18:03:22 +03:00
vloghtb bugfix in blif front-end 2015-05-18 11:15:49 +02:00