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yosys/techlibs/greenpak4
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Claire Xenia Wolf 72787f52fc Fixing old e-mail addresses and deadnames 
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
 		2021-06-08 00:39:36 +02:00
..
Makefile.inc Added blackbox $__COUNT_ cell model 2017-09-01 06:44:28 -07:00
cells_blackbox.v Added RESET_TO_MAX parameter to $__COUNT_ cell. Cannot yet be extracted. 2017-09-14 10:26:32 -07:00
cells_latch.v greenpak4: Can now techmap inferred D latches (without set/reset or output inverter) 2016-12-10 18:46:36 +08:00
cells_map.v Add force_downto and force_upto wire attributes. 2020-05-19 01:42:40 +02:00
cells_sim.v Refactoring: moved modules still in cells_sim to cells_sim_wip 2017-09-01 06:44:15 -07:00
cells_sim_ams.v Moved GP_POR out of digital cells b/c it has delays 2017-08-14 10:45:39 -07:00
cells_sim_digital.v Fixed typo in error message 2017-09-01 06:45:10 -07:00
cells_sim_wip.v Refactoring: moved modules still in cells_sim to cells_sim_wip 2017-09-01 06:44:15 -07:00
gp_dff.lib Fixed indenting in techlibs/greenpak4/gp_dff.lib 2016-03-29 13:44:14 +02:00
greenpak4_dffinv.cc Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
synth_greenpak4.cc Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00