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aiger
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switch argument order to work with macOS getopt
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2020-09-23 12:48:26 +02:00 |
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arch
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Update tests
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2023-06-09 14:41:45 +02:00 |
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asicworld
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Fix FIRRTL to Verilog process instance subfield assignment.
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2019-02-25 16:18:13 -08:00 |
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bind
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Add support for parsing the SystemVerilog 'bind' construct
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2021-07-16 09:31:39 -04:00 |
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blif
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Adding check for BLIF names command input plane size.
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2022-08-21 23:18:20 -05:00 |
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bram
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Fix the tests we just broke
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2021-12-10 00:22:37 +01:00 |
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errors
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Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,
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2018-10-25 02:37:56 +03:00 |
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fmt
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cxxrtl: add "-print-output" option, test in fmt
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2023-08-11 04:46:52 +02:00 |
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fsm
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tests: fsm to use a randomly-generated seed
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2020-04-24 14:31:33 -07:00 |
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hana
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Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests.
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2016-09-22 11:49:29 -06:00 |
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liberty
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fix file rights
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2023-05-17 13:39:57 +02:00 |
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lut
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Forgot to commit
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2019-07-16 12:44:26 -07:00 |
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memfile
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Added 'set -e' into tests/memfile/run-test.sh
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2020-02-06 10:45:40 -03:00 |
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memlib
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More tests in memlib/generate.py
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2023-02-21 05:23:15 +13:00 |
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memories
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Fix the tests we just broke
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2021-12-10 00:22:37 +01:00 |
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opt
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opt_expr: Fix 'signed X>=0' replacement for wide output ports
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2023-08-01 13:50:12 +01:00 |
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opt_share
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tests: Parallelize
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2020-09-21 15:07:02 +02:00 |
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proc
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proc_rom: Add special handling of const-0 address bits.
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2022-05-18 17:32:30 +02:00 |
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realmath
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Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests.
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2016-09-22 11:49:29 -06:00 |
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rpc
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rpc test: make frontend listen before launching yosys & introduce safeguard if yosys errors
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2020-03-06 15:29:01 +01:00 |
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sat
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Proper example code
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2022-03-14 15:39:11 +01:00 |
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select
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Merge pull request #1949 from YosysHQ/eddie/select_blackbox
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2020-04-22 15:35:05 -07:00 |
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share
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Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests.
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2016-09-22 11:49:29 -06:00 |
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sim
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Replace GNU specific invocation of basename(1) with the equivalent
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2022-10-23 11:02:18 +13:00 |
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simple
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verilog: Support module-scoped task/function calls
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2022-10-29 15:14:11 -04:00 |
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simple_abc9
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abc9: fix SCC issues (#2694)
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2021-03-29 22:01:57 -07:00 |
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smv
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Progress in SMV back-end
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2015-06-19 14:08:46 +02:00 |
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sva
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verific: Use new value change logic also for $stable of wide signals.
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2022-05-11 13:05:27 +02:00 |
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svinterfaces
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Resolve package types in interfaces (#3658)
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2023-02-12 18:25:39 -05:00 |
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svtypes
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Corrected handling of nested typedefs of struct/union
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2023-07-20 23:39:44 -04:00 |
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techmap
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tests: Extend aigmap.ys with SAT comparison
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2023-07-31 16:26:50 +02:00 |
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tools
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support file locations containing spaces
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2022-08-08 20:30:50 +02:00 |
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unit
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Build hotfix in tests/unit/Makefile
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2016-12-11 10:58:49 +01:00 |
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various
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ast: use new format string helpers.
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2023-08-11 04:46:52 +02:00 |
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verific
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verific: Fix enum_values support and signed attribute values
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2023-03-15 09:51:36 +01:00 |
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verilog
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Standard compliance for tests/verilog/block_labels.ys
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2023-05-21 16:38:14 -04:00 |
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vloghtb
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Use HTTPS for website links, gatecat email
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2021-06-09 12:16:56 +02:00 |
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xprop
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xprop tests: Make iverilog invocation more portable
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2023-02-13 16:54:11 +01:00 |
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gen-tests-makefile.sh
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Out of bounds checking for struct/union members
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2023-02-19 23:25:08 +01:00 |
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