yosys/tests
Claire Xen 0146d83ed8
Merge pull request #3014 from YosysHQ/claire/fix-vgtest
Fix "make vgtest"
2021-09-24 17:50:34 +02:00
..
aiger switch argument order to work with macOS getopt 2020-09-23 12:48:26 +02:00
arch abc9: replace cell type/parameters if derived type already processed (#2991) 2021-09-09 10:05:55 -07:00
asicworld
bind Add support for parsing the SystemVerilog 'bind' construct 2021-07-16 09:31:39 -04:00
blif tests/blif: Add missing gitignore 2021-05-20 12:49:51 +02:00
bram tests/bram: Do not generate write address collisions. 2021-03-08 16:53:03 +01:00
errors
fsm
hana
liberty dfflibmap: Refactor to use dfflegalize internally. 2020-07-09 18:51:03 +02:00
lut
memfile
memories Add opt_mem_widen pass. 2021-08-14 01:06:23 +02:00
opt memory_share: Add -nosat and -nowiden options. 2021-08-14 00:09:04 +02:00
opt_share tests: Parallelize 2020-09-21 15:07:02 +02:00
proc proc_prune: Make assign removal and promotion per-bit, remember promoted bits. 2021-08-14 15:26:11 +02:00
realmath
rpc
sat assertpmux: Fix crash on unused $pmux output. 2021-02-22 23:30:28 +01:00
select
share
simple Fix "make vgtest" so it runs to the end (but now it fails ;) 2021-09-23 14:54:28 +02:00
simple_abc9 abc9: fix SCC issues (#2694) 2021-03-29 22:01:57 -07:00
smv
sva
svinterfaces Add a test for interfaces on modules loaded on-demand 2021-07-14 22:54:50 -04:00
svtypes sv: improve support for wire and var with user-defined types 2021-08-12 22:41:41 -06:00
techmap abc9: make re-entrant (#2993) 2021-09-09 10:06:31 -07:00
tools memory_dff: Remove now-useless write port handling. 2021-03-08 20:16:29 +01:00
unit
various More deadname stuff 2021-06-09 12:40:33 +02:00
verilog sv: support wand and wor of data types 2021-09-21 14:52:28 -04:00
vloghtb Use HTTPS for website links, gatecat email 2021-06-09 12:16:56 +02:00
gen-tests-makefile.sh tests: Parallelize 2020-09-21 15:07:02 +02:00