This website requires JavaScript.
Explore
Help
Sign In
riscv
/
yosys
mirror of
https://github.com/YosysHQ/yosys.git
Watch
1
Star
0
Fork
You've already forked yosys
0
Code
Issues
Projects
Releases
Wiki
Activity
f6579282d7
yosys
/
passes
History
Siesh1oo
f7c2cf6fe2
- passes/abc/abc.cc: #include <cerrno> for errno; use POSIX getcwd() for portability (get_current_dir_name() does not exist on BSD).
2014-03-10 14:35:53 +01:00
..
abc
- passes/abc/abc.cc: #include <cerrno> for errno; use POSIX getcwd() for portability (get_current_dir_name() does not exist on BSD).
2014-03-10 14:35:53 +01:00
cmds
- passes/techmap/dfflibmap.cc, passes/fsm/fsm_recode.cc, passes/cmds/select.cc: #include <cerrno> for errno, use c++-style includes.
2014-03-10 14:35:46 +01:00
fsm
- passes/techmap/dfflibmap.cc, passes/fsm/fsm_recode.cc, passes/cmds/select.cc: #include <cerrno> for errno, use c++-style includes.
2014-03-10 14:35:46 +01:00
hierarchy
Implemented read_verilog -defer
2014-02-13 13:59:13 +01:00
memory
Fixed bug in collecting of RD_TRANSPARENT parameter in memory_collect
2014-02-08 19:13:19 +01:00
opt
Fixed undef handling in opt_reduce
2014-03-06 14:18:34 +01:00
proc
Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arst
2014-02-21 23:34:45 +01:00
sat
Fixed bug in freduce command
2014-03-07 18:44:23 +01:00
techmap
- passes/techmap/dfflibmap.cc, passes/fsm/fsm_recode.cc, passes/cmds/select.cc: #include <cerrno> for errno, use c++-style includes.
2014-03-10 14:35:46 +01:00