Clifford Wolf eb67a7532b Add $allconst and $allseq cell types ... Signed-off-by: Clifford Wolf <clifford@clifford.at>		2018-02-23 13:14:47 +01:00
..
.gitignore	Updated .gitignore file for ilang and verilog frontends	2014-10-15 01:14:38 +02:00
Makefile.inc	Adjust makefiles to work with out-of-tree builds	2015-08-12 15:04:44 +02:00
const2ast.cc	Fixed segfault on invalid verilog constant 1'b_	2015-09-22 08:13:09 +02:00
preproc.cc	Add support for "yosys -E"	2018-01-07 16:36:13 +01:00
verilog_frontend.cc	Bugfix in verilog_defaults argument parser	2017-12-24 17:21:37 +01:00
verilog_frontend.h	Remember global declarations and defines accross read_verilog calls	2016-11-15 12:42:43 +01:00
verilog_lexer.l	Add Verilog "automatic" keyword (ignored in synthesis)	2017-11-23 08:51:38 +01:00
verilog_parser.y	Add $allconst and $allseq cell types	2018-02-23 13:14:47 +01:00