Clifford Wolf ee9188a5b4 Added logic-loop error handling to freduce		2015-06-30 17:11:46 +02:00
..
cmds	Bugfix in chparam	2015-06-30 01:38:34 +02:00
equiv	Replaced ezDefaultSAT with ezSatPtr	2015-02-21 12:15:41 +01:00
fsm	Added $eq/$neq -> $logic_not/$reduce_bool optimization	2015-04-29 07:28:15 +02:00
hierarchy	Added "dffinit", Support for initialized Xilinx DFF	2015-04-04 19:00:15 +02:00
memory	Modernized memory_dff (and fixed a bug)	2015-06-14 16:15:51 +02:00
opt	Added opt_share -share_all	2015-05-31 14:24:34 +02:00
proc	Minor fixes in handling of "init" attribute	2015-04-09 15:12:26 +02:00
sat	Added logic-loop error handling to freduce	2015-06-30 17:11:46 +02:00
techmap	AigMaker refactoring	2015-06-10 23:00:12 +02:00
tests	Renamed "aig" to "aigmap"	2015-06-10 07:24:26 +02:00