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tests
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Improved xilinx "bram1" test
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2015-04-09 17:12:12 +02:00 |
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.gitignore
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Added support for initialized xilinx brams
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2015-04-06 17:07:10 +02:00 |
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Makefile.inc
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Add +/xilinx/cells_box.v containing models for ABC boxes
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2019-04-16 11:21:03 -07:00 |
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arith_map.v
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Changes required for VPR place and route synth_xilinx.
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2019-03-01 12:02:27 -08:00 |
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brams.txt
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Added read-enable to memory model
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2015-09-25 12:23:11 +02:00 |
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brams_bb.v
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Added Xilinx bram black-box modules
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2015-04-06 08:44:30 +02:00 |
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brams_init.py
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Squelch trailing whitespace, including meta-whitespace
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2018-03-11 16:03:41 +01:00 |
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brams_map.v
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Revert BRAM WRITE_MODE changes.
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2019-03-04 09:22:22 -08:00 |
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cells.box
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Make cells.box whiteboxes not blackboxes
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2019-04-16 12:43:14 -07:00 |
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cells.lut
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Fix spacing
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2019-04-16 13:16:20 -07:00 |
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cells_box.v
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Add +/xilinx/cells_box.v containing models for ABC boxes
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2019-04-16 11:21:03 -07:00 |
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cells_map.v
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Fix cells_map.v some more
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2019-04-11 10:48:14 -07:00 |
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cells_sim.v
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Revert "Add abc_box_id attribute to MUXF7/F8 cells"
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2019-04-16 11:14:59 -07:00 |
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cells_xtra.sh
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Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.
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2019-04-12 09:35:15 -07:00 |
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cells_xtra.v
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Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.
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2019-04-12 09:35:15 -07:00 |
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drams.txt
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Added memory_bram "make_outreg" feature
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2015-04-09 16:08:54 +02:00 |
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drams_map.v
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Xilinx DRAMS: RAM64X1D, RAM128X1D
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2015-04-09 13:37:07 +02:00 |
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ff_map.v
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Changes required for VPR place and route synth_xilinx.
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2019-03-01 12:02:27 -08:00 |
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lut_map.v
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Changes required for VPR place and route synth_xilinx.
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2019-03-01 12:02:27 -08:00 |
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synth_xilinx.cc
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read_verilog cells_box.v before techmap
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2019-04-16 12:41:56 -07:00 |
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