mirror of https://github.com/YosysHQ/yosys.git
5b779f7f4e
By instantiating the LUTRAM cell directly, we avoid a trip through altsyncram, which speeds up Quartus synthesis time. This also gives a little more flexibility, as Yosys can build RAMs out of individual 32x1 LUTRAM cells. While working on this, I discovered that the mem_init0 parameter of <family>_mlab_cell gets ignored by Quartus. |
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| .. | ||
| alm_map.v | ||
| alm_sim.v | ||
| arith_alm_map.v | ||
| bram_m10k.txt | ||
| bram_m10k_map.v | ||
| bram_m20k.txt | ||
| bram_m20k_map.v | ||
| dff_map.v | ||
| dff_sim.v | ||
| lutram_mlab.txt | ||
| megafunction_bb.v | ||
| mem_sim.v | ||
| quartus_rename.v | ||