| .. |
|
tests
|
Add pattern detection support for DSP48E1 model, check against vendor
|
2019-09-18 10:45:04 -07:00 |
|
.gitignore
|
Added support for initialized xilinx brams
|
2015-04-06 17:07:10 +02:00 |
|
Makefile.inc
|
Rename abc_* names/attributes to more precisely be abc9_*
|
2019-10-04 11:04:10 -07:00 |
|
abc9_map.v
|
Rename abc_* names/attributes to more precisely be abc9_*
|
2019-10-04 11:04:10 -07:00 |
|
abc9_model.v
|
Rename abc_* names/attributes to more precisely be abc9_*
|
2019-10-04 11:04:10 -07:00 |
|
abc9_unmap.v
|
Rename abc_* names/attributes to more precisely be abc9_*
|
2019-10-04 11:04:10 -07:00 |
|
abc9_xc7.box
|
Rename abc_* names/attributes to more precisely be abc9_*
|
2019-10-04 11:04:10 -07:00 |
|
abc9_xc7.lut
|
Rename abc_* names/attributes to more precisely be abc9_*
|
2019-10-04 11:04:10 -07:00 |
|
abc9_xc7_nowide.lut
|
Rename abc_* names/attributes to more precisely be abc9_*
|
2019-10-04 11:04:10 -07:00 |
|
arith_map.v
|
Instead of MUXCY/XORCY use CARRY4 (with timing)
|
2019-05-21 16:19:45 -07:00 |
|
brams_init.py
|
synth_xilinx: Initial Spartan 6 block RAM inference support.
|
2019-07-11 14:45:48 +02:00 |
|
cells_map.v
|
Use abc_{map,unmap,model}.v
|
2019-08-20 12:39:11 -07:00 |
|
cells_sim.v
|
xilinx: Add simulation model for IBUFG.
|
2019-10-10 13:16:03 +02:00 |
|
cells_xtra.py
|
xilinx: Add simulation model for IBUFG.
|
2019-10-10 13:16:03 +02:00 |
|
dsp_map.v
|
D is 25 bits not 24 bits wide
|
2019-09-19 15:55:49 -07:00 |
|
lut_map.v
|
Really permute Xilinx LUT mappings as default LUT6.I5:A6
|
2019-06-18 11:48:48 -07:00 |
|
lutrams.txt
|
Work in progress for renaming labels/options in synth_xilinx
|
2019-07-18 14:20:43 -07:00 |
|
lutrams_map.v
|
Work in progress for renaming labels/options in synth_xilinx
|
2019-07-18 14:20:43 -07:00 |
|
mux_map.v
|
Change synth_xilinx's -nomux to -minmuxf <int>
|
2019-06-24 10:04:01 -07:00 |
|
synth_xilinx.cc
|
Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9
|
2019-10-08 10:53:38 -07:00 |
|
xc6s_brams.txt
|
synth_xilinx: Initial Spartan 6 block RAM inference support.
|
2019-07-11 14:45:48 +02:00 |
|
xc6s_brams_bb.v
|
Rename abc_* names/attributes to more precisely be abc9_*
|
2019-10-04 11:04:10 -07:00 |
|
xc6s_brams_map.v
|
RST -> RSTBRST for RAMB8BWER
|
2019-07-29 16:05:44 -07:00 |
|
xc6s_cells_xtra.v
|
xilinx: Add simulation model for IBUFG.
|
2019-10-10 13:16:03 +02:00 |
|
xc6s_ff_map.v
|
synth_xilinx: Support latches, remove used-up FF init values.
|
2019-09-30 12:52:43 +02:00 |
|
xc6v_cells_xtra.v
|
xilinx: Add simulation model for IBUFG.
|
2019-10-10 13:16:03 +02:00 |
|
xc7_brams.txt
|
synth_xilinx: Initial Spartan 6 block RAM inference support.
|
2019-07-11 14:45:48 +02:00 |
|
xc7_brams_bb.v
|
Rename abc_* names/attributes to more precisely be abc9_*
|
2019-10-04 11:04:10 -07:00 |
|
xc7_brams_map.v
|
synth_xilinx: Initial Spartan 6 block RAM inference support.
|
2019-07-11 14:45:48 +02:00 |
|
xc7_cells_xtra.v
|
xilinx: Add simulation model for IBUFG.
|
2019-10-10 13:16:03 +02:00 |
|
xc7_ff_map.v
|
synth_xilinx: Support latches, remove used-up FF init values.
|
2019-09-30 12:52:43 +02:00 |
|
xcu_cells_xtra.v
|
Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}
|
2019-09-30 12:52:43 +02:00 |
526fe4cb89