mirror of https://github.com/YosysHQ/yosys.git
709 lines
30 KiB
Python
709 lines
30 KiB
Python
#!/usr/bin/env python3
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from argparse import ArgumentParser
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from io import StringIO
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from enum import Enum, auto
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import os.path
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import sys
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import re
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class Cell:
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def __init__(self, name, keep=False, port_attrs={}):
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self.name = name
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self.keep = keep
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self.port_attrs = port_attrs
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XC6S_CELLS = [
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# Design elements types listed in Xilinx UG615.
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# Advanced.
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Cell('MCB'),
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Cell('PCIE_A1'),
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# Arithmetic functions.
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Cell('DSP48A1', port_attrs={'CLK': ['clkbuf_sink']}),
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# Clock components.
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# Cell('BUFG', port_attrs={'O': ['clkbuf_driver']}),
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Cell('BUFGCE', port_attrs={'O': ['clkbuf_driver']}),
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Cell('BUFGCE_1', port_attrs={'O': ['clkbuf_driver']}),
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Cell('BUFGMUX', port_attrs={'O': ['clkbuf_driver']}),
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Cell('BUFGMUX_1', port_attrs={'O': ['clkbuf_driver']}),
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Cell('BUFH', port_attrs={'O': ['clkbuf_driver']}),
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Cell('BUFIO2', port_attrs={'IOCLK': ['clkbuf_driver'], 'DIVCLK': ['clkbuf_driver']}),
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Cell('BUFIO2_2CLK', port_attrs={'IOCLK': ['clkbuf_driver'], 'DIVCLK': ['clkbuf_driver']}),
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Cell('BUFIO2FB', port_attrs={'O': ['clkbuf_driver']}),
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Cell('BUFPLL_MCB', port_attrs={'IOCLK0': ['clkbuf_driver'], 'IOCLK1': ['clkbuf_driver']}),
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Cell('DCM_CLKGEN'),
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Cell('DCM_SP'),
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Cell('PLL_BASE'),
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# Config/BSCAN components.
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Cell('BSCAN_SPARTAN6', keep=True),
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Cell('DNA_PORT'),
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Cell('ICAP_SPARTAN6', keep=True),
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Cell('POST_CRC_INTERNAL'),
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Cell('STARTUP_SPARTAN6', keep=True),
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Cell('SUSPEND_SYNC', keep=True),
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# I/O components.
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Cell('GTPA1_DUAL'),
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# Cell('IBUF', port_attrs={'I': ['iopad_external_pin']}),
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Cell('IBUFDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
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Cell('IBUFDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
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# Cell('IBUFG', port_attrs={'I': ['iopad_external_pin']}),
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Cell('IBUFGDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
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Cell('IBUFGDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
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Cell('IOBUF', port_attrs={'IO': ['iopad_external_pin']}),
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Cell('IOBUFDS', port_attrs={'IO': ['iopad_external_pin']}),
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Cell('IODELAY2', port_attrs={'IOCLK0': ['clkbuf_sink'], 'IOCLK1': ['clkbuf_sink'], 'CLK': ['clkbuf_sink']}),
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Cell('IODRP2', port_attrs={'IOCLK0': ['clkbuf_sink'], 'IOCLK1': ['clkbuf_sink'], 'CLK': ['clkbuf_sink']}),
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Cell('IODRP2_MCB', port_attrs={'IOCLK0': ['clkbuf_sink'], 'IOCLK1': ['clkbuf_sink'], 'CLK': ['clkbuf_sink']}),
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Cell('ISERDES2', port_attrs={
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'CLK0': ['clkbuf_sink'],
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'CLK1': ['clkbuf_sink'],
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'CLKDIV': ['clkbuf_sink'],
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}),
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Cell('KEEPER'),
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# Cell('OBUF', port_attrs={'O': ['iopad_external_pin']}),
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Cell('OBUFDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
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Cell('OBUFT', port_attrs={'O': ['iopad_external_pin']}),
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Cell('OBUFTDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
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Cell('OSERDES2', port_attrs={
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'CLK0': ['clkbuf_sink'],
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'CLK1': ['clkbuf_sink'],
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'CLKDIV': ['clkbuf_sink'],
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}),
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Cell('PULLDOWN'),
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Cell('PULLUP'),
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# RAM/ROM.
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#Cell('RAM128X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
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# NOTE: not in the official library guide!
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Cell('RAM128X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
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Cell('RAM256X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
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Cell('RAM32M', port_attrs={'WCLK': ['clkbuf_sink']}),
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#Cell('RAM32X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
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Cell('RAM32X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
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Cell('RAM32X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
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Cell('RAM32X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
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Cell('RAM64M', port_attrs={'WCLK': ['clkbuf_sink']}),
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#Cell('RAM64X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
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Cell('RAM64X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
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Cell('RAM64X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
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# NOTE: not in the official library guide!
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Cell('RAM64X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
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# Cell('RAMB8BWER', port_attrs={'CLKAWRCLK': ['clkbuf_sink'], 'CLKBRDCLK': ['clkbuf_sink']}),
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# Cell('RAMB16BWER', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}),
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Cell('ROM128X1'),
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Cell('ROM256X1'),
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Cell('ROM32X1'),
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Cell('ROM64X1'),
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# Registers/latches.
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# Cell('FDCE'),
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# Cell('FDPE'),
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# Cell('FDRE'),
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# Cell('FDSE'),
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Cell('IDDR2', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink']}),
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# Cell('LDCE'),
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# Cell('LDPE'),
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Cell('ODDR2', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink']}),
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# Slice/CLB primitives.
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# Cell('CARRY4'),
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Cell('CFGLUT5', port_attrs={'CLK': ['clkbuf_sink']}),
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# Cell('LUT1'),
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# Cell('LUT2'),
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# Cell('LUT3'),
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# Cell('LUT4'),
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# Cell('LUT5'),
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# Cell('LUT6'),
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# Cell('LUT6_2'),
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# Cell('MUXF7'),
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# Cell('MUXF8'),
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# Cell('SRL16E', port_attrs={'CLK': ['clkbuf_sink']}),
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# Cell('SRLC32E', port_attrs={'CLK': ['clkbuf_sink']}),
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]
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XC6V_CELLS = [
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# Design elements types listed in Xilinx UG623.
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# Advanced.
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Cell('PCIE_2_0'),
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Cell('SYSMON'),
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# Arithmetic functions.
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#Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}),
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# Clock components.
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# Cell('BUFG', port_attrs={'O': ['clkbuf_driver']}),
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Cell('BUFGCE', port_attrs={'O': ['clkbuf_driver']}),
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Cell('BUFGCE_1', port_attrs={'O': ['clkbuf_driver']}),
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#Cell('BUFGCTRL', port_attrs={'O': ['clkbuf_driver']}),
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Cell('BUFGMUX', port_attrs={'O': ['clkbuf_driver']}),
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Cell('BUFGMUX_1', port_attrs={'O': ['clkbuf_driver']}),
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Cell('BUFGMUX_CTRL', port_attrs={'O': ['clkbuf_driver']}),
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Cell('BUFH', port_attrs={'O': ['clkbuf_driver']}),
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#Cell('BUFHCE', port_attrs={'O': ['clkbuf_driver']}),
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Cell('BUFIO', port_attrs={'O': ['clkbuf_driver']}),
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Cell('BUFIODQS', port_attrs={'O': ['clkbuf_driver']}),
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Cell('BUFR', port_attrs={'O': ['clkbuf_driver']}),
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Cell('IBUFDS_GTXE1', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
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Cell('MMCM_ADV'),
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Cell('MMCM_BASE'),
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# Config/BSCAN components.
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Cell('BSCAN_VIRTEX6', keep=True),
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Cell('CAPTURE_VIRTEX6', keep=True),
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Cell('DNA_PORT'),
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Cell('EFUSE_USR'),
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Cell('FRAME_ECC_VIRTEX6'),
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Cell('ICAP_VIRTEX6', keep=True),
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Cell('STARTUP_VIRTEX6', keep=True),
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Cell('USR_ACCESS_VIRTEX6'),
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# I/O components.
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Cell('DCIRESET', keep=True),
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Cell('GTHE1_QUAD'),
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Cell('GTXE1'),
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# Cell('IBUF', port_attrs={'I': ['iopad_external_pin']}),
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Cell('IBUFDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
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Cell('IBUFDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
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Cell('IBUFDS_GTHE1', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
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# Cell('IBUFG', port_attrs={'I': ['iopad_external_pin']}),
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Cell('IBUFGDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
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Cell('IBUFGDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
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Cell('IDELAYCTRL', keep=True, port_attrs={'REFCLK': ['clkbuf_sink']}),
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Cell('IOBUF', port_attrs={'IO': ['iopad_external_pin']}),
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Cell('IOBUFDS', port_attrs={'IO': ['iopad_external_pin']}),
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Cell('IODELAYE1', port_attrs={'C': ['clkbuf_sink']}),
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Cell('ISERDESE1', port_attrs={
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'CLK': ['clkbuf_sink'],
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'CLKB': ['clkbuf_sink'],
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'OCLK': ['clkbuf_sink'],
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'CLKDIV': ['clkbuf_sink'],
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}),
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Cell('KEEPER'),
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# Cell('OBUF', port_attrs={'O': ['iopad_external_pin']}),
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Cell('OBUFDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
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Cell('OBUFT', port_attrs={'O': ['iopad_external_pin']}),
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Cell('OBUFTDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
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Cell('OSERDESE1', port_attrs={'CLK': ['clkbuf_sink'], 'CLKDIV': ['clkbuf_sink']}),
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Cell('PULLDOWN'),
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Cell('PULLUP'),
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Cell('TEMAC_SINGLE'),
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# RAM/ROM.
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Cell('FIFO18E1', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
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Cell('FIFO36E1', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
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#Cell('RAM128X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
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Cell('RAM128X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
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Cell('RAM256X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
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Cell('RAM32M', port_attrs={'WCLK': ['clkbuf_sink']}),
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#Cell('RAM32X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
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Cell('RAM32X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
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Cell('RAM32X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
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Cell('RAM32X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
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Cell('RAM64M', port_attrs={'WCLK': ['clkbuf_sink']}),
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#Cell('RAM64X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
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Cell('RAM64X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
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Cell('RAM64X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
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# NOTE: not in the official library guide!
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Cell('RAM64X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
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# Cell('RAMB18E1', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}),
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# Cell('RAMB36E1', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}),
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Cell('ROM128X1'),
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Cell('ROM256X1'),
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Cell('ROM32X1'),
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Cell('ROM64X1'),
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# Registers/latches.
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# Cell('FDCE'),
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# Cell('FDPE'),
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# Cell('FDRE'),
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# Cell('FDSE'),
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Cell('IDDR', port_attrs={'C': ['clkbuf_sink']}),
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Cell('IDDR_2CLK', port_attrs={'C': ['clkbuf_sink'], 'CB': ['clkbuf_sink']}),
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Cell('LDCE'),
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Cell('LDPE'),
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Cell('ODDR', port_attrs={'C': ['clkbuf_sink']}),
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# Slice/CLB primitives.
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# Cell('CARRY4'),
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Cell('CFGLUT5', port_attrs={'CLK': ['clkbuf_sink']}),
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# Cell('LUT1'),
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# Cell('LUT2'),
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# Cell('LUT3'),
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# Cell('LUT4'),
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# Cell('LUT5'),
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# Cell('LUT6'),
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# Cell('LUT6_2'),
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# Cell('MUXF7'),
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# Cell('MUXF8'),
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# Cell('SRL16E', port_attrs={'CLK': ['clkbuf_sink']}),
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# Cell('SRLC32E', port_attrs={'CLK': ['clkbuf_sink']}),
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]
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XC7_CELLS = [
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# Design elements types listed in Xilinx UG953.
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# Advanced.
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Cell('GTHE2_CHANNEL'),
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Cell('GTHE2_COMMON'),
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Cell('GTPE2_CHANNEL'),
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Cell('GTPE2_COMMON'),
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Cell('GTXE2_CHANNEL'),
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Cell('GTXE2_COMMON'),
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Cell('PCIE_2_1'),
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Cell('PCIE_3_0'),
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Cell('XADC'),
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# Arithmetic functions.
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#Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}),
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# Clock components.
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# Cell('BUFG', port_attrs={'O': ['clkbuf_driver']}),
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Cell('BUFGCE', port_attrs={'O': ['clkbuf_driver']}),
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Cell('BUFGCE_1', port_attrs={'O': ['clkbuf_driver']}),
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#Cell('BUFGCTRL', port_attrs={'O': ['clkbuf_driver']}),
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Cell('BUFGMUX', port_attrs={'O': ['clkbuf_driver']}),
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Cell('BUFGMUX_1', port_attrs={'O': ['clkbuf_driver']}),
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Cell('BUFGMUX_CTRL', port_attrs={'O': ['clkbuf_driver']}),
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Cell('BUFH', port_attrs={'O': ['clkbuf_driver']}),
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#Cell('BUFHCE', port_attrs={'O': ['clkbuf_driver']}),
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Cell('BUFIO', port_attrs={'O': ['clkbuf_driver']}),
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Cell('BUFMR', port_attrs={'O': ['clkbuf_driver']}),
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Cell('BUFMRCE', port_attrs={'O': ['clkbuf_driver']}),
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Cell('BUFR', port_attrs={'O': ['clkbuf_driver']}),
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Cell('MMCME2_ADV'),
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Cell('MMCME2_BASE'),
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Cell('PLLE2_ADV'),
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Cell('PLLE2_BASE'),
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# Config/BSCAN components.
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Cell('BSCANE2', keep=True),
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Cell('CAPTUREE2', keep=True),
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Cell('DNA_PORT'),
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Cell('EFUSE_USR'),
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Cell('FRAME_ECCE2'),
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Cell('ICAPE2', keep=True),
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Cell('STARTUPE2', keep=True),
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Cell('USR_ACCESSE2'),
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# I/O components.
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Cell('DCIRESET', keep=True),
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# Cell('IBUF', port_attrs={'I': ['iopad_external_pin']}),
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Cell('IBUF_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin']}),
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Cell('IBUF_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin']}),
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Cell('IBUFDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
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Cell('IBUFDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
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Cell('IBUFDS_DIFF_OUT_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
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Cell('IBUFDS_DIFF_OUT_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
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Cell('IBUFDS_GTE2', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
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Cell('IBUFDS_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
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Cell('IBUFDS_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
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# Cell('IBUFG', port_attrs={'I': ['iopad_external_pin']}),
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Cell('IBUFGDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
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Cell('IBUFGDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
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Cell('IDELAYCTRL', keep=True, port_attrs={'REFCLK': ['clkbuf_sink']}),
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Cell('IDELAYE2', port_attrs={'C': ['clkbuf_sink']}),
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Cell('IN_FIFO', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
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Cell('IOBUF', port_attrs={'IO': ['iopad_external_pin']}),
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Cell('IOBUF_DCIEN', port_attrs={'IO': ['iopad_external_pin']}),
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Cell('IOBUF_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin']}),
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Cell('IOBUFDS', port_attrs={'IO': ['iopad_external_pin']}),
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Cell('IOBUFDS_DCIEN', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
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Cell('IOBUFDS_DIFF_OUT', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
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Cell('IOBUFDS_DIFF_OUT_DCIEN', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
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Cell('IOBUFDS_DIFF_OUT_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
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Cell('IOBUFDS_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
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Cell('ISERDESE2', port_attrs={
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'CLK': ['clkbuf_sink'],
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'CLKB': ['clkbuf_sink'],
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'OCLK': ['clkbuf_sink'],
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'OCLKB': ['clkbuf_sink'],
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'CLKDIV': ['clkbuf_sink'],
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'CLKDIVP': ['clkbuf_sink'],
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}),
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Cell('KEEPER'),
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# Cell('OBUF', port_attrs={'O': ['iopad_external_pin']}),
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Cell('OBUFDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
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Cell('OBUFT', port_attrs={'O': ['iopad_external_pin']}),
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Cell('OBUFTDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
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Cell('ODELAYE2', port_attrs={'C': ['clkbuf_sink']}),
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Cell('OSERDESE2', port_attrs={'CLK': ['clkbuf_sink'], 'CLKDIV': ['clkbuf_sink']}),
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Cell('OUT_FIFO', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
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Cell('PHASER_IN'),
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Cell('PHASER_IN_PHY'),
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Cell('PHASER_OUT'),
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Cell('PHASER_OUT_PHY'),
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Cell('PHASER_REF'),
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Cell('PHY_CONTROL'),
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Cell('PULLDOWN'),
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Cell('PULLUP'),
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# RAM/ROM.
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Cell('FIFO18E1', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
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|
Cell('FIFO36E1', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
|
|
#Cell('RAM128X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
|
|
Cell('RAM128X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
|
|
Cell('RAM256X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
|
|
Cell('RAM32M', port_attrs={'WCLK': ['clkbuf_sink']}),
|
|
#Cell('RAM32X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
|
|
Cell('RAM32X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
|
|
Cell('RAM32X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
|
|
Cell('RAM32X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
|
|
Cell('RAM64M', port_attrs={'WCLK': ['clkbuf_sink']}),
|
|
#Cell('RAM64X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
|
|
Cell('RAM64X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
|
|
Cell('RAM64X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
|
|
# NOTE: not in the official library guide!
|
|
Cell('RAM64X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
|
|
# Cell('RAMB18E1', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}),
|
|
# Cell('RAMB36E1', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}),
|
|
Cell('ROM128X1'),
|
|
Cell('ROM256X1'),
|
|
Cell('ROM32X1'),
|
|
Cell('ROM64X1'),
|
|
|
|
# Registers/latches.
|
|
# Cell('FDCE'),
|
|
# Cell('FDPE'),
|
|
# Cell('FDRE'),
|
|
# Cell('FDSE'),
|
|
Cell('IDDR', port_attrs={'C': ['clkbuf_sink']}),
|
|
Cell('IDDR_2CLK', port_attrs={'C': ['clkbuf_sink'], 'CB': ['clkbuf_sink']}),
|
|
Cell('LDCE'),
|
|
Cell('LDPE'),
|
|
Cell('ODDR', port_attrs={'C': ['clkbuf_sink']}),
|
|
|
|
# Slice/CLB primitives.
|
|
# Cell('CARRY4'),
|
|
Cell('CFGLUT5', port_attrs={'CLK': ['clkbuf_sink']}),
|
|
# Cell('LUT1'),
|
|
# Cell('LUT2'),
|
|
# Cell('LUT3'),
|
|
# Cell('LUT4'),
|
|
# Cell('LUT5'),
|
|
# Cell('LUT6'),
|
|
# Cell('LUT6_2'),
|
|
# Cell('MUXF7'),
|
|
# Cell('MUXF8'),
|
|
# Cell('SRL16E', port_attrs={'CLK': ['clkbuf_sink']}),
|
|
# Cell('SRLC32E', port_attrs={'CLK': ['clkbuf_sink']}),
|
|
|
|
# NOTE: not in the official library guide!
|
|
Cell('PS7', keep=True),
|
|
]
|
|
|
|
|
|
XCU_CELLS = [
|
|
# Design elements types listed in Xilinx UG974.
|
|
|
|
# Advanced.
|
|
Cell('CMAC'),
|
|
Cell('CMACE4'),
|
|
Cell('GTHE3_CHANNEL'),
|
|
Cell('GTHE3_COMMON'),
|
|
Cell('GTHE4_CHANNEL'),
|
|
Cell('GTHE4_COMMON'),
|
|
Cell('GTYE3_CHANNEL'),
|
|
Cell('GTYE3_COMMON'),
|
|
Cell('GTYE4_CHANNEL'),
|
|
Cell('GTYE4_COMMON'),
|
|
Cell('IBUFDS_GTE3', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
|
Cell('IBUFDS_GTE4', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
|
Cell('ILKN'),
|
|
Cell('ILKNE4'),
|
|
Cell('OBUFDS_GTE3', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
|
|
Cell('OBUFDS_GTE3_ADV', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
|
|
Cell('OBUFDS_GTE4', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
|
|
Cell('OBUFDS_GTE4_ADV', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
|
|
Cell('PCIE40E4'),
|
|
Cell('PCIE_3_1'),
|
|
Cell('SYSMONE1'),
|
|
Cell('SYSMONE4'),
|
|
|
|
# Arithmetic functions.
|
|
Cell('DSP48E2', port_attrs={'CLK': ['clkbuf_sink']}),
|
|
|
|
# Blockram.
|
|
Cell('FIFO18E2', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
|
|
Cell('FIFO36E2', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
|
|
Cell('RAMB18E2', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}),
|
|
Cell('RAMB36E2', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}),
|
|
Cell('URAM288', port_attrs={'CLK': ['clkbuf_sink']}),
|
|
Cell('URAM288_BASE', port_attrs={'CLK': ['clkbuf_sink']}),
|
|
|
|
# CLB.
|
|
# Cell('LUT6_2'),
|
|
#Cell('RAM128X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
|
|
Cell('RAM128X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
|
|
Cell('RAM256X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
|
|
Cell('RAM256X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
|
|
Cell('RAM32M', port_attrs={'WCLK': ['clkbuf_sink']}),
|
|
Cell('RAM32M16', port_attrs={'WCLK': ['clkbuf_sink']}),
|
|
#Cell('RAM32X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
|
|
Cell('RAM32X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
|
|
Cell('RAM512X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
|
|
Cell('RAM64M', port_attrs={'WCLK': ['clkbuf_sink']}),
|
|
Cell('RAM64M8', port_attrs={'WCLK': ['clkbuf_sink']}),
|
|
#Cell('RAM64X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
|
|
Cell('RAM64X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
|
|
Cell('AND2B1L'),
|
|
Cell('CARRY8'),
|
|
Cell('CFGLUT5', port_attrs={'CLK': ['clkbuf_sink']}),
|
|
# Cell('LUT1'),
|
|
# Cell('LUT2'),
|
|
# Cell('LUT3'),
|
|
# Cell('LUT4'),
|
|
# Cell('LUT5'),
|
|
# Cell('LUT6'),
|
|
# Cell('MUXF7'),
|
|
# Cell('MUXF8'),
|
|
Cell('MUXF9'),
|
|
Cell('OR2L'),
|
|
# Cell('SRL16E', port_attrs={'CLK': ['clkbuf_sink']}),
|
|
# Cell('SRLC32E', port_attrs={'CLK': ['clkbuf_sink']}),
|
|
|
|
# Clock.
|
|
# Cell('BUFG', port_attrs={'O': ['clkbuf_driver']}),
|
|
Cell('BUFG_GT', port_attrs={'O': ['clkbuf_driver']}),
|
|
Cell('BUFG_GT_SYNC'),
|
|
Cell('BUFG_PS', port_attrs={'O': ['clkbuf_driver']}),
|
|
Cell('BUFGCE', port_attrs={'O': ['clkbuf_driver']}),
|
|
Cell('BUFGCE_1', port_attrs={'O': ['clkbuf_driver']}),
|
|
Cell('BUFGCE_DIV', port_attrs={'O': ['clkbuf_driver']}),
|
|
#Cell('BUFGCTRL', port_attrs={'O': ['clkbuf_driver']}),
|
|
Cell('BUFGMUX', port_attrs={'O': ['clkbuf_driver']}),
|
|
Cell('BUFGMUX_1', port_attrs={'O': ['clkbuf_driver']}),
|
|
Cell('BUFGMUX_CTRL', port_attrs={'O': ['clkbuf_driver']}),
|
|
Cell('MMCME3_ADV'),
|
|
Cell('MMCME3_BASE'),
|
|
Cell('MMCME4_ADV'),
|
|
Cell('MMCME4_BASE'),
|
|
Cell('PLLE3_ADV'),
|
|
Cell('PLLE3_BASE'),
|
|
Cell('PLLE4_ADV'),
|
|
Cell('PLLE4_BASE'),
|
|
|
|
# Configuration.
|
|
Cell('BSCANE2', keep=True),
|
|
Cell('DNA_PORTE2'),
|
|
Cell('EFUSE_USR'),
|
|
Cell('FRAME_ECCE3'),
|
|
Cell('ICAPE3', keep=True),
|
|
Cell('MASTER_JTAG', keep=True),
|
|
Cell('STARTUPE3', keep=True),
|
|
Cell('USR_ACCESSE2'),
|
|
|
|
# I/O.
|
|
Cell('BITSLICE_CONTROL', keep=True),
|
|
Cell('DCIRESET', keep=True),
|
|
Cell('HPIO_VREF'),
|
|
# XXX
|
|
# Cell('IBUF', port_attrs={'I': ['iopad_external_pin']}),
|
|
Cell('IBUF_ANALOG', port_attrs={'I': ['iopad_external_pin']}),
|
|
Cell('IBUF_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin']}),
|
|
Cell('IBUF_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin']}),
|
|
Cell('IBUFDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
|
Cell('IBUFDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
|
Cell('IBUFDS_DIFF_OUT_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
|
Cell('IBUFDS_DIFF_OUT_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
|
Cell('IBUFDS_DPHY', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
|
Cell('IBUFDS_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
|
Cell('IBUFDS_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
|
Cell('IBUFDSE3', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
|
Cell('IBUFE3', port_attrs={'I': ['iopad_external_pin']}),
|
|
Cell('IDELAYCTRL', keep=True, port_attrs={'REFCLK': ['clkbuf_sink']}),
|
|
Cell('IDELAYE3', port_attrs={'CLK': ['clkbuf_sink']}),
|
|
Cell('IOBUF', port_attrs={'IO': ['iopad_external_pin']}),
|
|
Cell('IOBUF_DCIEN', port_attrs={'IO': ['iopad_external_pin']}),
|
|
Cell('IOBUF_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin']}),
|
|
Cell('IOBUFDS', port_attrs={'IO': ['iopad_external_pin']}),
|
|
Cell('IOBUFDS_DCIEN', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
|
|
Cell('IOBUFDS_DIFF_OUT', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
|
|
Cell('IOBUFDS_DIFF_OUT_DCIEN', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
|
|
Cell('IOBUFDS_DIFF_OUT_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
|
|
Cell('IOBUFDS_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
|
|
Cell('IOBUFDSE3', port_attrs={'IO': ['iopad_external_pin']}),
|
|
Cell('IOBUFE3', port_attrs={'IO': ['iopad_external_pin']}),
|
|
Cell('ISERDESE3', port_attrs={
|
|
'CLK': ['clkbuf_sink'],
|
|
'CLK_B': ['clkbuf_sink'],
|
|
'FIFO_RD_CLK': ['clkbuf_sink'],
|
|
'CLKDIV': ['clkbuf_sink'],
|
|
}),
|
|
Cell('KEEPER'),
|
|
# Cell('OBUF', port_attrs={'O': ['iopad_external_pin']}),
|
|
Cell('OBUFDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
|
|
Cell('OBUFDS_DPHY', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
|
|
Cell('OBUFT', port_attrs={'O': ['iopad_external_pin']}),
|
|
Cell('OBUFTDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
|
|
Cell('ODELAYE3', port_attrs={'CLK': ['clkbuf_sink']}),
|
|
Cell('OSERDESE3', port_attrs={'CLK': ['clkbuf_sink'], 'CLKDIV': ['clkbuf_sink']}),
|
|
Cell('PULLDOWN'),
|
|
Cell('PULLUP'),
|
|
Cell('RIU_OR'),
|
|
Cell('RX_BITSLICE'),
|
|
Cell('RXTX_BITSLICE'),
|
|
Cell('TX_BITSLICE'),
|
|
Cell('TX_BITSLICE_TRI'),
|
|
|
|
# Registers.
|
|
# Cell('FDCE'),
|
|
# Cell('FDPE'),
|
|
# Cell('FDRE'),
|
|
# Cell('FDSE'),
|
|
Cell('HARD_SYNC', port_attrs={'CLK': ['clkbuf_sink']}),
|
|
Cell('IDDRE1', port_attrs={'C': ['clkbuf_sink'], 'CB': ['clkbuf_sink']}),
|
|
Cell('LDCE'),
|
|
Cell('LDPE'),
|
|
Cell('ODDRE1', port_attrs={'C': ['clkbuf_sink']}),
|
|
|
|
# NOTE: not in the official library guide!
|
|
Cell('PS8', keep=True),
|
|
]
|
|
|
|
|
|
class State(Enum):
|
|
OUTSIDE = auto()
|
|
IN_MODULE = auto()
|
|
IN_OTHER_MODULE = auto()
|
|
IN_FUNCTION = auto()
|
|
IN_TASK = auto()
|
|
|
|
def xtract_cell_decl(cell, dirs, outf):
|
|
for dir in dirs:
|
|
fname = os.path.join(dir, cell.name + '.v')
|
|
try:
|
|
with open(fname) as f:
|
|
state = State.OUTSIDE
|
|
found = False
|
|
# Probably the most horrible Verilog "parser" ever written.
|
|
module_ports = []
|
|
invertible_ports = set()
|
|
for l in f:
|
|
l = l.partition('//')[0]
|
|
l = l.strip()
|
|
if l == 'module {}'.format(cell.name) or l.startswith('module {} '.format(cell.name)):
|
|
if found:
|
|
print('Multiple modules in {}.'.format(fname))
|
|
sys.exit(1)
|
|
elif state != State.OUTSIDE:
|
|
print('Nested modules in {}.'.format(fname))
|
|
sys.exit(1)
|
|
found = True
|
|
state = State.IN_MODULE
|
|
if cell.keep:
|
|
outf.write('(* keep *)\n')
|
|
outf.write('module {} (...);\n'.format(cell.name))
|
|
elif l.startswith('module '):
|
|
if state != State.OUTSIDE:
|
|
print('Nested modules in {}.'.format(fname))
|
|
sys.exit(1)
|
|
state = State.IN_OTHER_MODULE
|
|
elif l.startswith('task '):
|
|
if state == State.IN_MODULE:
|
|
state = State.IN_TASK
|
|
elif l.startswith('function '):
|
|
if state == State.IN_MODULE:
|
|
state = State.IN_FUNCTION
|
|
elif l == 'endtask':
|
|
if state == State.IN_TASK:
|
|
state = State.IN_MODULE
|
|
elif l == 'endfunction':
|
|
if state == State.IN_FUNCTION:
|
|
state = State.IN_MODULE
|
|
elif l == 'endmodule':
|
|
if state == State.IN_MODULE:
|
|
for kind, rng, port in module_ports:
|
|
for attr in cell.port_attrs.get(port, []):
|
|
outf.write(' (* {} *)\n'.format(attr))
|
|
if port in invertible_ports:
|
|
outf.write(' (* invertible_pin = "IS_{}_INVERTED" *)\n'.format(port))
|
|
if rng is None:
|
|
outf.write(' {} {};\n'.format(kind, port))
|
|
else:
|
|
outf.write(' {} {} {};\n'.format(kind, rng, port))
|
|
outf.write(l + '\n')
|
|
outf.write('\n')
|
|
elif state != State.IN_OTHER_MODULE:
|
|
print('endmodule in weird place in {}.'.format(cell.name, fname))
|
|
sys.exit(1)
|
|
state = State.OUTSIDE
|
|
elif l.startswith(('input ', 'output ', 'inout ')) and state == State.IN_MODULE:
|
|
if l.endswith((';', ',')):
|
|
l = l[:-1]
|
|
if ';' in l:
|
|
print('Weird port line in {} [{}].'.format(fname, l))
|
|
sys.exit(1)
|
|
kind, _, ports = l.partition(' ')
|
|
for port in ports.split(','):
|
|
port = port.strip()
|
|
if port.startswith('['):
|
|
rng, port = port.split()
|
|
else:
|
|
rng = None
|
|
module_ports.append((kind, rng, port))
|
|
elif l.startswith('parameter ') and state == State.IN_MODULE:
|
|
if 'UNPLACED' in l:
|
|
continue
|
|
if l.endswith((';', ',')):
|
|
l = l[:-1]
|
|
while ' ' in l:
|
|
l = l.replace(' ', ' ')
|
|
if ';' in l:
|
|
print('Weird parameter line in {} [{}].'.format(fname, l))
|
|
sys.exit(1)
|
|
outf.write(' {};\n'.format(l))
|
|
match = re.search('IS_([a-zA-Z0-9_]+)_INVERTED', l)
|
|
if match:
|
|
invertible_ports.add(match[1])
|
|
if state != State.OUTSIDE:
|
|
print('endmodule not found in {}.'.format(fname))
|
|
sys.exit(1)
|
|
if not found:
|
|
print('Cannot find module {} in {}.'.format(cell.name, fname))
|
|
sys.exit(1)
|
|
return
|
|
except FileNotFoundError:
|
|
continue
|
|
print('Cannot find {}.'.format(cell.name))
|
|
sys.exit(1)
|
|
|
|
if __name__ == '__main__':
|
|
parser = ArgumentParser(description='Extract Xilinx blackbox cell definitions from ISE and Vivado.')
|
|
parser.add_argument('vivado_dir', nargs='?', default='/opt/Xilinx/Vivado/2018.1')
|
|
parser.add_argument('ise_dir', nargs='?', default='/opt/Xilinx/ISE/14.7')
|
|
args = parser.parse_args()
|
|
|
|
dirs = [
|
|
os.path.join(args.vivado_dir, 'data/verilog/src/xeclib'),
|
|
os.path.join(args.vivado_dir, 'data/verilog/src/retarget'),
|
|
os.path.join(args.ise_dir, 'ISE_DS/ISE/verilog/xeclib/unisims'),
|
|
]
|
|
for dir in dirs:
|
|
if not os.path.isdir(dir):
|
|
print('{} is not a directory'.format(dir))
|
|
|
|
for ofile, cells in [
|
|
('xc6s_cells_xtra.v', XC6S_CELLS),
|
|
('xc6v_cells_xtra.v', XC6V_CELLS),
|
|
('xc7_cells_xtra.v', XC7_CELLS),
|
|
('xcu_cells_xtra.v', XCU_CELLS),
|
|
]:
|
|
out = StringIO()
|
|
for cell in cells:
|
|
xtract_cell_decl(cell, dirs, out)
|
|
|
|
with open(ofile, 'w') as f:
|
|
f.write('// Created by cells_xtra.py from Xilinx models\n')
|
|
f.write('\n')
|
|
f.write(out.getvalue())
|