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Eddie Hung de79978372
xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325) 
* xilinx: eliminate SCCs from DSP48E1 model

* xilinx: add SCC test for DSP48E1

* Update techlibs/xilinx/cells_sim.v

* xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1

Have a test that checks it works through ABC9 when enabled
 		2020-09-23 09:15:24 -07:00
..
aiger switch argument order to work with macOS getopt 2020-09-23 12:48:26 +02:00
arch xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325) 2020-09-23 09:15:24 -07:00
asicworld Fix FIRRTL to Verilog process instance subfield assignment. 2019-02-25 16:18:13 -08:00
bram Added support for (single-clock) transparent memories to bram tests 2016-11-01 10:03:13 +01:00
errors Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique, 2018-10-25 02:37:56 +03:00
fsm tests: fsm to use a randomly-generated seed 2020-04-24 14:31:33 -07:00
hana Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests. 2016-09-22 11:49:29 -06:00
liberty dfflibmap: Refactor to use dfflegalize internally. 2020-07-09 18:51:03 +02:00
lut Forgot to commit 2019-07-16 12:44:26 -07:00
memfile Added 'set -e' into tests/memfile/run-test.sh 2020-02-06 10:45:40 -03:00
memories memory_dff: Fix checking of feedback mux input when more than one mux 2019-07-02 13:35:50 +01:00
opt Merge pull request #2344 from YosysHQ/mwk/opt_share-fixes 2020-08-20 16:24:53 +02:00
opt_share Support various binary operators in opt_share 2019-08-04 19:06:38 +02:00
proc proc_clean: fix order of switch insertion. 2019-08-19 16:44:23 +00:00
realmath Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests. 2016-09-22 11:49:29 -06:00
rpc rpc test: make frontend listen before launching yosys & introduce safeguard if yosys errors 2020-03-06 15:29:01 +01:00
sat satgen: Add support for dffe, sdff, sdffe, sdffce cells. 2020-07-24 03:19:21 +02:00
select Merge pull request #1949 from YosysHQ/eddie/select_blackbox 2020-04-22 15:35:05 -07:00
share Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests. 2016-09-22 11:49:29 -06:00
simple Module name scope support 2020-08-20 20:15:08 -04:00
simple_abc9 abc9: test to use box file instead of auto 2020-05-14 10:33:56 -07:00
smv Progress in SMV back-end 2015-06-19 14:08:46 +02:00
sva Fix "verific -extnets" for more complex situations 2019-03-26 14:17:46 +01:00
svinterfaces Fix typo in tests/svinterfaces/runone.sh 2019-05-03 14:40:51 +02:00
svtypes Merge pull request #2329 from antmicro/arrays-fix-multirange-size 2020-09-17 18:27:05 +02:00
techmap flatten, techmap: don't canonicalize tpl driven bits via sigmap. 2020-08-26 16:29:42 +00:00
tools Replace opt_rmdff with opt_dff. 2020-08-07 13:21:03 +02:00
unit Build hotfix in tests/unit/Makefile 2016-12-11 10:58:49 +01:00
various Merge pull request #2352 from zachjs/const-func-localparam 2020-09-01 17:31:48 +02:00
verilog Merge pull request #2080 from YosysHQ/eddie/fix_test_warnings 2020-06-03 08:37:07 -07:00
vloghtb bugfix in blif front-end 2015-05-18 11:15:49 +02:00