This website requires JavaScript.
Explore
Help
Sign In
riscv
/
yosys
mirror of
https://github.com/YosysHQ/yosys.git
Watch
1
Star
0
Fork
You've already forked yosys
0
Code
Issues
Projects
Releases
Wiki
Activity
dd5dc06863
yosys
/
passes
History
Jannis Harder
7c818d30f7
sim: Bring $print trigger/sampling semantics in line with FFs
2024-01-25 16:21:03 +01:00
..
cmds
Fix typo in stat help
2024-01-21 16:32:05 -05:00
equiv
equiv_simple: Fix seed handling in non-short mode
2023-10-03 13:05:42 +02:00
fsm
add option to fsm_detect to ignore self-resetting
2023-01-30 16:12:53 +01:00
hierarchy
hierarchy: keep display statements, like formal assertions.
2024-01-22 10:09:22 +00:00
memory
Fix printf formats
2024-01-15 12:07:54 +01:00
opt
opt_lut: Replace `-dlogic` with `-tech ice40`
2024-01-15 12:35:21 +01:00
pmgen
peepopt: Fix padding for the peepopt_shiftmul_right pattern
2023-12-06 18:35:44 +01:00
proc
proc_clean: only consider fully-defined switch operands too.
2023-08-12 02:46:31 +02:00
sat
sim: Bring $print trigger/sampling semantics in line with FFs
2024-01-25 16:21:03 +01:00
techmap
booth: Redo baseline architecture summation
2023-11-22 15:47:11 +01:00
tests
Add $bmux and $demux cells.
2022-01-28 23:34:41 +01:00