mirror of https://github.com/YosysHQ/yosys.git
equiv_simple: Fix seed handling in non-short mode
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dbf11da50a
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1f1f43edd9
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@ -133,11 +133,9 @@ struct EquivSimpleWorker
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for (auto bit_a : seed_a)
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find_input_cone(next_seed_a, full_cells_cone_a, full_bits_cone_a, no_stop_cells, no_stop_bits, nullptr, bit_a);
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next_seed_a.clear();
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for (auto bit_b : seed_b)
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find_input_cone(next_seed_b, full_cells_cone_b, full_bits_cone_b, no_stop_cells, no_stop_bits, nullptr, bit_b);
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next_seed_b.clear();
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pool<Cell*> short_cells_cone_a, short_cells_cone_b;
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pool<SigBit> short_bits_cone_a, short_bits_cone_b;
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@ -145,10 +143,12 @@ struct EquivSimpleWorker
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if (short_cones)
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{
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next_seed_a.clear();
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for (auto bit_a : seed_a)
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find_input_cone(next_seed_a, short_cells_cone_a, short_bits_cone_a, full_cells_cone_b, full_bits_cone_b, &input_bits, bit_a);
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next_seed_a.swap(seed_a);
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next_seed_b.clear();
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for (auto bit_b : seed_b)
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find_input_cone(next_seed_b, short_cells_cone_b, short_bits_cone_b, full_cells_cone_a, full_bits_cone_a, &input_bits, bit_b);
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next_seed_b.swap(seed_b);
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