mirror of https://github.com/YosysHQ/yosys.git
equiv_simple: Do not special-case flip-flop types in cone expansion
If there's an asynchronous flip-flop type, it will be caught by not having a synchronous SAT model later on. Otherwise we can support all flip-flops.
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@ -60,7 +60,7 @@ struct EquivSimpleWorker
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for (auto &conn : cell->connections())
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if (yosys_celltypes.cell_input(cell->type, conn.first))
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for (auto bit : sigmap(conn.second)) {
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if (cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_), ID($ff), ID($_FF_))) {
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if (RTLIL::builtin_ff_cell_types().count(cell->type)) {
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if (!conn.first.in(ID::CLK, ID::C))
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next_seed.insert(bit);
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} else
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