Miodrag Milanovic ea0b6258ab Simulation model verilog fix		2019-06-26 18:34:34 +02:00
..
tests	Improved xilinx "bram1" test	2015-04-09 17:12:12 +02:00
.gitignore	Added support for initialized xilinx brams	2015-04-06 17:07:10 +02:00
Makefile.inc	Changes required for VPR place and route synth_xilinx.	2019-03-01 12:02:27 -08:00
arith_map.v	Changes required for VPR place and route synth_xilinx.	2019-03-01 12:02:27 -08:00
brams.txt	Added read-enable to memory model	2015-09-25 12:23:11 +02:00
brams_bb.v	Added Xilinx bram black-box modules	2015-04-06 08:44:30 +02:00
brams_init.py	Squelch trailing whitespace, including meta-whitespace	2018-03-11 16:03:41 +01:00
brams_map.v	Revert BRAM WRITE_MODE changes.	2019-03-04 09:22:22 -08:00
cells_map.v	Rename cells_map.v to prevent clash with ff_map.v	2019-05-03 14:40:32 -07:00
cells_sim.v	Simulation model verilog fix	2019-06-26 18:34:34 +02:00
cells_xtra.sh	Add RAM32X1D support	2019-06-24 16:16:50 -07:00
cells_xtra.v	Add RAM32X1D support	2019-06-24 16:16:50 -07:00
drams.txt	Add RAM32X1D support	2019-06-24 16:16:50 -07:00
drams_map.v	Add RAM32X1D support	2019-06-24 16:16:50 -07:00
ff_map.v	Move neg-pol to pos-pol mapping from ff_map to cells_map.v	2019-04-28 12:36:04 -07:00
lut_map.v	Changes required for VPR place and route synth_xilinx.	2019-03-01 12:02:27 -08:00
synth_xilinx.cc	Remove extra newline	2019-06-03 20:04:47 -07:00