Miodrag Milanovic ea0b6258ab Simulation model verilog fix		2019-06-26 18:34:34 +02:00
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achronix	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
anlogic	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
common	Add "wreduce -keepdc", fixes #1016	2019-05-20 15:36:13 +02:00
coolrunner2	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
easic	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
ecp5	Simulation model verilog fix	2019-06-26 18:34:34 +02:00
gowin	Merge branch 'master' of https://github.com/dh73/yosys_gowin into dh73-master	2019-04-22 09:09:27 +02:00
greenpak4	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
ice40	Fixed small typo in ice40_unlut help summary	2019-06-19 16:39:46 -04:00
intel	Fix formatting for synth_intel.cc	2019-05-09 08:40:05 -07:00
sf2	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
xilinx	Simulation model verilog fix	2019-06-26 18:34:34 +02:00
.gitignore	added .gitignore files	2013-01-05 11:19:11 +01:00