yosys/frontends/ilang
whitequark 93bc5affd3 Allow attributes on individual switch cases in RTLIL.
The parser changes are slightly awkward. Consider the following IL:

    process $0
      <point 1>
      switch \foo
        <point 2>
        case 1'1
          assign \bar \baz
          <point 3>
          ...
        case
      end
    end

Before this commit, attributes are valid in <point 1>, and <point 3>
iff it is immediately followed by a `switch`. (They are essentially
attached to the switch.) But, after this commit, and because switch
cases do not have an ending delimiter, <point 3> becomes ambiguous:
the attribute could attach to either the following `case`, or to
the following `switch`. This isn't expressible in LALR(1) and results
in a reduce/reduce conflict.

To address this, attributes inside processes are now valid anywhere
inside the process: in <point 1> and <point 3> a part of case body,
and in <point 2> as a separate rule. As a consequence, attributes
can now precede `assign`s, which is made illegal in the same way it
is illegal to attach attributes to `connect`.

Attributes are tracked separately from the parser state, so this
does not affect collection of attributes at all, other than allowing
them on `case`s. The grammar change serves purely to allow attributes
in more syntactic places.
2019-07-08 11:34:58 +00:00
..
.gitignore Add "make coverage" 2018-08-27 14:22:21 +02:00
Makefile.inc Add "make coverage" 2018-08-27 14:22:21 +02:00
ilang_frontend.cc Add "read_ilang -lib" 2019-04-05 17:31:49 +02:00
ilang_frontend.h Add "read_ilang -lib" 2019-04-05 17:31:49 +02:00
ilang_lexer.l Add "real" keyword to ilang format 2019-05-06 12:00:40 +02:00
ilang_parser.y Allow attributes on individual switch cases in RTLIL. 2019-07-08 11:34:58 +00:00