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Clifford Wolf 8da0888bf6 Fix handling of read_verilog config in AstModule::reprocess_module(), fixes #1360 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 		2019-09-20 12:16:20 +02:00
..
aiger Merge pull request #1355 from YosysHQ/eddie/peepopt_dffmuxext 2019-09-18 12:40:08 -07:00
ast Fix handling of read_verilog config in AstModule::reprocess_module(), fixes #1360 2019-09-20 12:16:20 +02:00
blif Change signature of parse_blif to take IdString 2019-08-15 10:26:24 -07:00
ilang Allow attributes on individual switch cases in RTLIL. 2019-07-08 11:34:58 +00:00
json Update JSON front-end to process new attr/param encoding 2019-08-01 12:48:22 +02:00
liberty stoi -> atoi 2019-08-07 11:09:17 -07:00
verific Fix erroneous ifndef-NDEBUG in verific.cc 2019-08-17 14:49:55 +02:00
verilog Fix handling of z_digit "?" and fix optimization of cmp with "z" 2019-09-13 13:39:39 +02:00