Clifford Wolf 777f2881d8 Add Verilog "automatic" keyword (ignored in synthesis)		2017-11-23 08:51:38 +01:00
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.gitignore	Updated .gitignore file for ilang and verilog frontends	2014-10-15 01:14:38 +02:00
Makefile.inc	Adjust makefiles to work with out-of-tree builds	2015-08-12 15:04:44 +02:00
const2ast.cc	Fixed segfault on invalid verilog constant 1'b_	2015-09-22 08:13:09 +02:00
preproc.cc	Accommodate Windows-style paths during include-file processing.	2017-11-14 16:16:24 -05:00
verilog_frontend.cc	Add a paragraph about pre-defined macros to read_verilog help message	2017-07-21 14:34:53 +02:00
verilog_frontend.h	Remember global declarations and defines accross read_verilog calls	2016-11-15 12:42:43 +01:00
verilog_lexer.l	Add Verilog "automatic" keyword (ignored in synthesis)	2017-11-23 08:51:38 +01:00
verilog_parser.y	Add Verilog "automatic" keyword (ignored in synthesis)	2017-11-23 08:51:38 +01:00