Marcelina Kościelnicka 9a4f420b4b Replace opt_rmdff with opt_dff.		2020-08-07 13:21:03 +02:00
..
aiger	tests: aiger test for wire->start_offset != 0	2020-05-02 10:00:32 -07:00
arch	Replace opt_rmdff with opt_dff.	2020-08-07 13:21:03 +02:00
asicworld	Fix FIRRTL to Verilog process instance subfield assignment.	2019-02-25 16:18:13 -08:00
bram	…
errors	…
fsm	tests: fsm to use a randomly-generated seed	2020-04-24 14:31:33 -07:00
hana	…
liberty	dfflibmap: Refactor to use dfflegalize internally.	2020-07-09 18:51:03 +02:00
lut	Forgot to commit	2019-07-16 12:44:26 -07:00
memfile	…
memories	…
opt	Add opt_dff pass.	2020-07-30 18:27:04 +02:00
opt_share	…
proc	…
realmath	…
rpc	rpc test: make frontend listen before launching yosys & introduce safeguard if yosys errors	2020-03-06 15:29:01 +01:00
sat	satgen: Add support for dffe, sdff, sdffe, sdffce cells.	2020-07-24 03:19:21 +02:00
select	Merge pull request #1949 from YosysHQ/eddie/select_blackbox	2020-04-22 15:35:05 -07:00
share	…
simple	Expand tests/simple/constmuldivmod.v	2020-05-28 22:59:04 +02:00
simple_abc9	abc9: test to use box file instead of auto	2020-05-14 10:33:56 -07:00
smv	…
sva	…
svinterfaces	…
svtypes	static cast: add tests	2020-06-19 17:40:38 -07:00
techmap	Add dffunmap pass.	2020-07-31 00:59:51 +02:00
tools	Replace opt_rmdff with opt_dff.	2020-08-07 13:21:03 +02:00
unit	…
various	Merge pull request #2306 from YosysHQ/mwk/equiv_induct-undef	2020-07-28 12:56:22 +02:00
verilog	Merge pull request #2080 from YosysHQ/eddie/fix_test_warnings	2020-06-03 08:37:07 -07:00
vloghtb	…