..
choices
techmap: Note down iteration in Kogge-Stone
2024-04-08 16:45:40 +02:00
.gitignore
Added first help messages for cell types
2015-10-14 16:27:42 +02:00
Makefile.inc
techmap: Split out Kogge-Stone into a separate file
2024-03-27 11:07:24 +01:00
abc9_map.v
techmap: Add support for [] wildcards in techmap_celltype.
2020-08-02 22:46:48 +02:00
abc9_model.v
abc9: fix SCC issues ( #2694 )
2021-03-29 22:01:57 -07:00
abc9_unmap.v
abc9: fix SCC issues ( #2694 )
2021-03-29 22:01:57 -07:00
adff2dff.v
Fix syntax error in adff2dff.v
2021-02-24 01:07:34 +01:00
cellhelp.py
cellhelp: Add source line to help
2024-10-15 07:16:40 +13:00
cells.lib
Added cells.lib
2015-01-16 15:50:42 +01:00
cmp2lcu.v
verilog: significant block scoping improvements
2021-01-31 09:42:09 -05:00
cmp2lut.v
verilog: significant block scoping improvements
2021-01-31 09:42:09 -05:00
cmp2softlogic.v
techlibs: Add `cmp2softlogic.v` to common
2023-11-13 10:42:12 +01:00
dff2ff.v
Add force_downto and force_upto wire attributes.
2020-05-19 01:42:40 +02:00
gate2lut.v
Fix invalid verilog syntax
2020-03-14 14:33:44 +01:00
gen_fine_ffs.py
Add $aldff and $aldffe: flip-flops with async load.
2021-10-02 18:12:52 +02:00
mul2dsp.v
Fix files with CRLF line endings
2021-06-09 12:16:33 +02:00
pmux2mux.v
Added techlibs/common/pmux2mux.v
2014-01-17 20:06:15 +01:00
prep.cc
Run `future` as part of `prep`
2023-09-13 11:32:36 +02:00
simcells.v
Add $aldff and $aldffe: flip-flops with async load.
2021-10-02 18:12:52 +02:00
simlib.v
cellhelp: Rename short_desc to title
2024-10-15 07:16:39 +13:00
smtmap.v
Add smtmap.v describing the smt2 backend's behavior for undef bits
2022-10-20 15:48:18 +02:00
synth.cc
synth: Fix out-of-sync help message
2024-03-06 14:55:43 +01:00
techmap.v
quicklogic: Avoid carry chains in division mapping
2024-09-19 12:18:47 +02:00
a2b2904ed8