yosys/backends
Clifford Wolf 9f4fbc5e74 Add <modname>_init() function generator to simpleC back-end 2017-05-16 19:34:07 +02:00
..
aiger Add write_aiger $anyseq support 2017-03-02 16:39:48 +01:00
blif Added wire start_offset and upto handling BLIF back-end 2016-11-23 13:54:33 +01:00
btor Added "yosys -D" feature 2016-04-21 23:28:37 +02:00
edif Add generation of logic cells to EDIF back-end runtest.py 2017-03-19 14:57:40 +01:00
firrtl More progress on Firrtl backend. 2017-02-13 11:17:53 -08:00
ilang Added avail params to ilang format, check module params in 'hierarchy -check' 2016-10-22 11:05:49 +02:00
intersynth Added "yosys -D" feature 2016-04-21 23:28:37 +02:00
json Improved write_json help message 2016-12-29 12:13:29 +01:00
simplec Add <modname>_init() function generator to simpleC back-end 2017-05-16 19:34:07 +02:00
smt2 Fix boolector support in yosys-smtbmc 2017-05-08 14:33:22 +02:00
smv Added "yosys -D" feature 2016-04-21 23:28:37 +02:00
spice Also escape "=" in spice output 2016-05-20 16:43:13 +02:00
verilog Cleanups and fixed in write_verilog regarding reg init 2016-11-16 12:00:39 +01:00