yosys/tests/arch/common
Miodrag Milanovic 9bd9db56c8 Unify verilog style 2019-10-18 12:50:24 +02:00
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add_sub.v Unify verilog style 2019-10-18 12:50:24 +02:00
adffs.v Unify verilog style 2019-10-18 12:50:24 +02:00
counter.v Unify verilog style 2019-10-18 12:50:24 +02:00
dffs.v Unify verilog style 2019-10-18 12:50:24 +02:00
fsm.v Unify verilog style 2019-10-18 12:50:24 +02:00
latches.v Unify verilog style 2019-10-18 12:50:24 +02:00
logic.v Unify verilog style 2019-10-18 12:50:24 +02:00
memory.v Common memory test now shared 2019-10-18 12:33:35 +02:00
mul.v Unify verilog style 2019-10-18 12:50:24 +02:00
mux.v Unify verilog style 2019-10-18 12:50:24 +02:00
shifter.v Unify verilog style 2019-10-18 12:50:24 +02:00
tribuf.v Unify verilog style 2019-10-18 12:50:24 +02:00