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yosys/tests/arch
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Miodrag Milanovic 9bd9db56c8 Unify verilog style 2019-10-18 12:50:24 +02:00
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anlogic Common memory test now shared 2019-10-18 12:33:35 +02:00
common Unify verilog style 2019-10-18 12:50:24 +02:00
ecp5 Common memory test now shared 2019-10-18 12:33:35 +02:00
efinix Common memory test now shared 2019-10-18 12:33:35 +02:00
ice40 Common memory test now shared 2019-10-18 12:33:35 +02:00
xilinx Common memory test now shared 2019-10-18 12:33:35 +02:00
run-test.sh Add simcells.v, simlib.v, and some output 2019-06-27 11:13:49 -07:00