yosys/tests
Rupert Swarbrick 414154dd27 Add support for parsing the SystemVerilog 'bind' construct
This doesn't do anything useful yet: the patch just adds support for
the syntax to the lexer and parser and adds some tests to check the
syntax parses properly. This generates AST nodes, but doesn't yet
generate RTLIL.

Since our existing hierarchical_identifier parser doesn't allow bit
selects (so you can't do something like foo[1].bar[2].baz), I've also
not added support for a trailing bit select (the "constant_bit_select"
non-terminal in "bind_target_instance" in the spec). If we turn out to
need this in future, we'll want to augment hierarchical_identifier and
its other users too.

Note that you can't easily use the BNF from the spec:

    bind_directive ::=
        "bind" bind_target_scope [ : bind_target_instance_list]
               bind_instantiation ;
      | "bind" bind_target_instance bind_instantiation ;

even if you fix the lookahead problem, because code like this matches
both branches in the BNF:

    bind a b b_i (.*);

The problem is that 'a' could either be a module name or a degenerate
hierarchical reference. This seems to be a genuine syntactic
ambiguity, which the spec resolves (p739) by saying that we have to
wait until resolution time (the hierarchy pass) and take whatever is
defined, treating 'a' as an instance name if it names both an instance
and a module.

To keep the parser simple, it currently accepts this invalid syntax:

    bind a.b : c d e (.*);

This is invalid because we're in the first branch of the BNF above, so
the "a.b" term should match bind_target_scope: a module or interface
identifier, not an arbitrary hierarchical identifier.

This will fail in the hierarchy pass (when it's implemented in a
future patch).
2021-07-16 09:31:39 -04:00
..
aiger switch argument order to work with macOS getopt 2020-09-23 12:48:26 +02:00
arch Fix files with CRLF line endings 2021-06-09 12:16:33 +02:00
asicworld Fix FIRRTL to Verilog process instance subfield assignment. 2019-02-25 16:18:13 -08:00
bind Add support for parsing the SystemVerilog 'bind' construct 2021-07-16 09:31:39 -04:00
blif tests/blif: Add missing gitignore 2021-05-20 12:49:51 +02:00
bram tests/bram: Do not generate write address collisions. 2021-03-08 16:53:03 +01:00
errors Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique, 2018-10-25 02:37:56 +03:00
fsm tests: fsm to use a randomly-generated seed 2020-04-24 14:31:33 -07:00
hana Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests. 2016-09-22 11:49:29 -06:00
liberty dfflibmap: Refactor to use dfflegalize internally. 2020-07-09 18:51:03 +02:00
lut Forgot to commit 2019-07-16 12:44:26 -07:00
memfile Added 'set -e' into tests/memfile/run-test.sh 2020-02-06 10:45:40 -03:00
memories tests: Parallelize 2020-09-21 15:07:02 +02:00
opt Add regression test for #2824. 2021-06-11 12:06:35 +01:00
opt_share tests: Parallelize 2020-09-21 15:07:02 +02:00
proc proc_arst: Add special-casing of clock signal in conditionals. 2021-03-15 17:17:29 +01:00
realmath Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests. 2016-09-22 11:49:29 -06:00
rpc rpc test: make frontend listen before launching yosys & introduce safeguard if yosys errors 2020-03-06 15:29:01 +01:00
sat assertpmux: Fix crash on unused $pmux output. 2021-02-22 23:30:28 +01:00
select Merge pull request #1949 from YosysHQ/eddie/select_blackbox 2020-04-22 15:35:05 -07:00
share Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests. 2016-09-22 11:49:29 -06:00
simple sv: fix up end label checking 2021-06-16 21:48:05 -04:00
simple_abc9 abc9: fix SCC issues (#2694) 2021-03-29 22:01:57 -07:00
smv Progress in SMV back-end 2015-06-19 14:08:46 +02:00
sva Fix "verific -extnets" for more complex situations 2019-03-26 14:17:46 +01:00
svinterfaces Add a test for interfaces on modules loaded on-demand 2021-07-14 22:54:50 -04:00
svtypes verilog: check entire user type stack for type definition 2021-03-21 19:35:13 -04:00
techmap Add tests for some common techmap files. 2021-02-24 01:07:34 +01:00
tools memory_dff: Remove now-useless write port handling. 2021-03-08 20:16:29 +01:00
unit Build hotfix in tests/unit/Makefile 2016-12-11 10:58:49 +01:00
various More deadname stuff 2021-06-09 12:40:33 +02:00
verilog sv: fix two struct access bugs 2021-07-15 11:57:20 -04:00
vloghtb Use HTTPS for website links, gatecat email 2021-06-09 12:16:56 +02:00
gen-tests-makefile.sh tests: Parallelize 2020-09-21 15:07:02 +02:00