Dan Ravensloft 1a07b330f8 intel_alm: Add multiply signedness to cells ... Quartus assumes unsigned multiplication by default, breaking signed multiplies, so add an input signedness parameter to the MISTRAL_MUL* cells to propagate to Quartus' <family>_mac cells.		2020-08-26 22:50:16 +02:00
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aiger	tests: aiger test for wire->start_offset != 0	2020-05-02 10:00:32 -07:00
arch	intel_alm: Add multiply signedness to cells	2020-08-26 22:50:16 +02:00
asicworld	Fix FIRRTL to Verilog process instance subfield assignment.	2019-02-25 16:18:13 -08:00
bram	…
errors	…
fsm	tests: fsm to use a randomly-generated seed	2020-04-24 14:31:33 -07:00
hana	…
liberty	dfflibmap: Refactor to use dfflegalize internally.	2020-07-09 18:51:03 +02:00
lut	…
memfile	Added 'set -e' into tests/memfile/run-test.sh	2020-02-06 10:45:40 -03:00
memories	…
opt	Merge pull request #2344 from YosysHQ/mwk/opt_share-fixes	2020-08-20 16:24:53 +02:00
opt_share	…
proc	proc_clean: fix order of switch insertion.	2019-08-19 16:44:23 +00:00
realmath	…
rpc	rpc test: make frontend listen before launching yosys & introduce safeguard if yosys errors	2020-03-06 15:29:01 +01:00
sat	satgen: Add support for dffe, sdff, sdffe, sdffce cells.	2020-07-24 03:19:21 +02:00
select	Merge pull request #1949 from YosysHQ/eddie/select_blackbox	2020-04-22 15:35:05 -07:00
share	…
simple	Merge pull request #2339 from zachjs/display-format-0s	2020-08-18 17:39:01 +02:00
simple_abc9	abc9: test to use box file instead of auto	2020-05-14 10:33:56 -07:00
smv	…
sva	…
svinterfaces	…
svtypes	Merge pull request #2122 from PeterCrozier/struct_array2	2020-08-19 17:58:37 +02:00
techmap	Merge pull request #2347 from YosysHQ/mwk/techmap-shift-fixes	2020-08-20 16:25:56 +02:00
tools	Replace opt_rmdff with opt_dff.	2020-08-07 13:21:03 +02:00
unit	…
various	Merge pull request #2328 from YosysHQ/mwk/opt_dff-cleanup	2020-08-20 16:21:58 +02:00
verilog	Merge pull request #2080 from YosysHQ/eddie/fix_test_warnings	2020-06-03 08:37:07 -07:00
vloghtb	…