mirror of https://github.com/YosysHQ/yosys.git
a33acb7cd9
This commit achieves three roughly equally important goals: 1. To bring the rendering code in kernel/fmt.cc and in cxxrtl.h as close together as possible, with an ideal of only having the bigint library as the difference between the render functions. 2. To make the treatment of `$time` and `$realtime` in CXXRTL closer to the Verilog semantics, at least in the formatting code. 3. To change the code generator so that all of the `$print`-to-`string` conversion code is contained inside of a closure. There are two reasons to aim for goal (3): a. Because output redirection through definition of a global ostream object is neither convenient nor useful for environments where the output is consumed by other code rather than being printed on a terminal. b. Because it may be desirable to, in some cases, ignore the `$print` cells that are present in the netlist based on a runtime decision. This is doubly true for an upcoming `$check` cell implementing assertions, since failing a `$check` would by default cause a crash. |
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.. | ||
aiger | ||
arch | ||
asicworld | ||
bind | ||
blif | ||
bram | ||
cxxrtl | ||
errors | ||
fmt | ||
fsm | ||
hana | ||
liberty | ||
lut | ||
memfile | ||
memlib | ||
memories | ||
opt | ||
opt_share | ||
proc | ||
realmath | ||
rpc | ||
sat | ||
select | ||
share | ||
sim | ||
simple | ||
simple_abc9 | ||
smv | ||
sva | ||
svinterfaces | ||
svtypes | ||
techmap | ||
tools | ||
unit | ||
various | ||
verific | ||
verilog | ||
vloghtb | ||
xprop | ||
gen-tests-makefile.sh |