mirror of https://github.com/YosysHQ/yosys.git
5467fe563a
Although logically two separate steps, these were treated as one for historic reasons. Splitting the two makes it possible to have designs that are only 2× slower than fastest possible (and are without extra delta cycles) that allow probing all public wires. |
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| aiger | ||
| blif | ||
| btor | ||
| cxxrtl | ||
| edif | ||
| firrtl | ||
| ilang | ||
| intersynth | ||
| json | ||
| protobuf | ||
| simplec | ||
| smt2 | ||
| smv | ||
| spice | ||
| table | ||
| verilog | ||