Xiretza edd8ff2c07 Add flooring division operator ... The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $divfloor cell provides this flooring division. This commit also fixes the handling of $div in opt_expr, which was previously optimized as if it was $divfloor.		2020-05-28 22:59:04 +02:00
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Makefile.inc	initial import	2013-01-05 11:13:26 +01:00
verilog_backend.cc	Add flooring division operator	2020-05-28 22:59:04 +02:00