| .. |
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aiger
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switch argument order to work with macOS getopt
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2020-09-23 12:48:26 +02:00 |
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arch
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FfData: some refactoring.
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2021-10-07 04:24:06 +02:00 |
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asicworld
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Fix FIRRTL to Verilog process instance subfield assignment.
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2019-02-25 16:18:13 -08:00 |
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bind
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Add support for parsing the SystemVerilog 'bind' construct
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2021-07-16 09:31:39 -04:00 |
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blif
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tests/blif: Add missing gitignore
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2021-05-20 12:49:51 +02:00 |
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bram
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tests/bram: Do not generate write address collisions.
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2021-03-08 16:53:03 +01:00 |
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errors
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Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,
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2018-10-25 02:37:56 +03:00 |
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fsm
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tests: fsm to use a randomly-generated seed
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2020-04-24 14:31:33 -07:00 |
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hana
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Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests.
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2016-09-22 11:49:29 -06:00 |
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liberty
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dfflibmap: Refactor to use dfflegalize internally.
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2020-07-09 18:51:03 +02:00 |
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lut
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Forgot to commit
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2019-07-16 12:44:26 -07:00 |
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memfile
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Added 'set -e' into tests/memfile/run-test.sh
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2020-02-06 10:45:40 -03:00 |
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memories
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Fix a regression from #3035.
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2021-10-08 15:44:07 +02:00 |
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opt
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extract_reduce: Refactor and fix input signal construction.
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2021-10-21 04:10:01 +02:00 |
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opt_share
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tests: Parallelize
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2020-09-21 15:07:02 +02:00 |
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proc
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proc_prune: Make assign removal and promotion per-bit, remember promoted bits.
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2021-08-14 15:26:11 +02:00 |
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realmath
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Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests.
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2016-09-22 11:49:29 -06:00 |
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rpc
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rpc test: make frontend listen before launching yosys & introduce safeguard if yosys errors
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2020-03-06 15:29:01 +01:00 |
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sat
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assertpmux: Fix crash on unused $pmux output.
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2021-02-22 23:30:28 +01:00 |
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select
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Merge pull request #1949 from YosysHQ/eddie/select_blackbox
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2020-04-22 15:35:05 -07:00 |
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share
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Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests.
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2016-09-22 11:49:29 -06:00 |
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simple
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verilog: use derived module info to elaborate cell connections
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2021-10-25 18:25:50 -07:00 |
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simple_abc9
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abc9: fix SCC issues (#2694)
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2021-03-29 22:01:57 -07:00 |
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smv
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Progress in SMV back-end
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2015-06-19 14:08:46 +02:00 |
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sva
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Fix "verific -extnets" for more complex situations
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2019-03-26 14:17:46 +01:00 |
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svinterfaces
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Add a test for interfaces on modules loaded on-demand
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2021-07-14 22:54:50 -04:00 |
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svtypes
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sv: improve support for wire and var with user-defined types
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2021-08-12 22:41:41 -06:00 |
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techmap
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dfflegalize: Add tests for aldff lowering.
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2021-10-27 14:14:01 +02:00 |
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tools
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Fixes in vcdcd.pl for newer Perl versions
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2021-10-19 10:56:43 +02:00 |
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unit
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Build hotfix in tests/unit/Makefile
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2016-12-11 10:58:49 +01:00 |
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various
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More deadname stuff
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2021-06-09 12:40:33 +02:00 |
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verilog
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verilog: use derived module info to elaborate cell connections
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2021-10-25 18:25:50 -07:00 |
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vloghtb
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Use HTTPS for website links, gatecat email
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2021-06-09 12:16:56 +02:00 |
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gen-tests-makefile.sh
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tests: Parallelize
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2020-09-21 15:07:02 +02:00 |
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