yosys/techlibs/common
Clifford Wolf 6c05badc43 New techmap default rules for $shr $sshr $shl $sshl 2014-07-30 18:49:12 +02:00
..
Makefile.inc Added "make PRETTY=1" 2014-07-24 17:15:01 +02:00
blackbox.sed Renamed stdcells_sim.v to simcells.v and fixed blackbox.v 2013-11-24 20:44:00 +01:00
pmux2mux.v Added techlibs/common/pmux2mux.v 2014-01-17 20:06:15 +01:00
simcells.v Added support for dlatchsr cells 2014-03-31 14:14:40 +02:00
simlib.v Bugfix in simlib.v for iverilog 2014-07-29 19:23:31 +02:00
stdcells.v New techmap default rules for $shr $sshr $shl $sshl 2014-07-30 18:49:12 +02:00