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7daad40ca4
yosys
/
techlibs
History
Clifford Wolf
6c05badc43
New techmap default rules for $shr $sshr $shl $sshl
2014-07-30 18:49:12 +02:00
..
cmos
Added test comments to techlibs/cmos/cmos_cells.lib
2014-01-29 10:51:02 +01:00
common
New techmap default rules for $shr $sshr $shl $sshl
2014-07-30 18:49:12 +02:00
xilinx
Added "make PRETTY=1"
2014-07-24 17:15:01 +02:00
.gitignore
added .gitignore files
2013-01-05 11:19:11 +01:00