mirror of https://github.com/YosysHQ/yosys.git
742ec78ca3
Fifo code based on SBY quick start. Instead of showing the full design we are (currently) focusing on a single output (rdata), using `%ci*` to get the subcircuit it relies on. |
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.. | ||
axis | ||
extensions | ||
fifo | ||
intro | ||
macc | ||
scrambler | ||
selections | ||
show | ||
stubnets | ||
synth_flow | ||
techmap | ||
.gitignore | ||
primetest.v |