mirror of https://github.com/YosysHQ/yosys.git
docs: more tidying
Fix 010 pdf link. Swap yosys script code blocks for literal includes. Fix broken example code.
This commit is contained in:
Krystine Sherwin
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@ -29,7 +29,7 @@ Download
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========
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This document was originally published in April 2015:
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:download:`Converting Verilog to BLIF PDF</_downloads/APPNOTE_012_Verilog_to_BTOR.pdf>`
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:download:`Converting Verilog to BLIF PDF</_downloads/APPNOTE_010_Verilog_to_BLIF.pdf>`
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..
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Installation
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@ -1,24 +1,32 @@
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# ============================================================================
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# part a
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read_verilog macc_xilinx_test.v
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read_verilog -lib -icells macc_xilinx_unwrap_map.v
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read_verilog -lib -icells macc_xilinx_xmap.v
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hierarchy -check ;;
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# end part a
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show -prefix macc_xilinx_test1a -format dot -notitle test1
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show -prefix macc_xilinx_test2a -format dot -notitle test2
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# ============================================================================
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# part b
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techmap -map macc_xilinx_swap_map.v;;
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# end part b
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show -prefix macc_xilinx_test1b -format dot -notitle test1
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show -prefix macc_xilinx_test2b -format dot -notitle test2
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# ============================================================================
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# part c
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techmap -map macc_xilinx_wrap_map.v
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connwrappers -unsigned $__mul_wrapper Y Y_WIDTH \
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-unsigned $__add_wrapper Y Y_WIDTH;;
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# end part c
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show -prefix macc_xilinx_test1c -format dot -notitle test1
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show -prefix macc_xilinx_test2c -format dot -notitle test2
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# ============================================================================
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# part d
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design -push
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read_verilog macc_xilinx_xmap.v
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techmap -map macc_xilinx_swap_map.v
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@ -29,12 +37,14 @@ design -pop
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extract -constports -ignore_parameters \
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-map %__macc_xilinx_xmap \
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-swap $__add_wrapper A,B ;;
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# end part d
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show -prefix macc_xilinx_test1d -format dot -notitle test1
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show -prefix macc_xilinx_test2d -format dot -notitle test2
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# ============================================================================
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# part e
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techmap -map macc_xilinx_unwrap_map.v;;
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# end part e
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show -prefix macc_xilinx_test1e -format dot -notitle test1
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show -prefix macc_xilinx_test2e -format dot -notitle test2
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@ -424,7 +424,7 @@ Yosys script for ASIC synthesis of the Amber ARMv2 CPU.
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if (ARST)
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Q <= ARST_VALUE;
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else
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<= D;
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Q <= D;
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endmodule
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@ -41,15 +41,23 @@ The extract pass
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.. todo:: add/expand supporting text
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.. literalinclude:: /code_examples/macc/macc_simple_test.ys
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:language: yoscrypt
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:lines: 1-2
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.. figure:: /_images/code_examples/macc/macc_simple_test_00a.*
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:class: width-helper
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before `extract`
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before :cmd:ref:`extract`
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.. literalinclude:: /code_examples/macc/macc_simple_test.ys
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:language: yoscrypt
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:lines: 6
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.. figure:: /_images/code_examples/macc/macc_simple_test_00b.*
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:class: width-helper
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after `extract`
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after :cmd:ref:`extract`
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.. literalinclude:: /code_examples/macc/macc_simple_test.v
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:language: verilog
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@ -59,13 +67,6 @@ The extract pass
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:language: verilog
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:caption: ``docs/source/code_examples/macc/macc_simple_xmap.v``
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.. code:: yoscrypt
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read_verilog macc_simple_test.v
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hierarchy -check -top test
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extract -map macc_simple_xmap.v;;
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.. literalinclude:: /code_examples/macc/macc_simple_test_01.v
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:language: verilog
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:caption: ``docs/source/code_examples/macc/macc_simple_test_01.v``
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@ -191,14 +192,10 @@ Wrapping in ``test1``:
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.. figure:: /_images/code_examples/macc/macc_xilinx_test1b.*
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:class: width-helper
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.. code:: yoscrypt
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techmap -map macc_xilinx_wrap_map.v
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connwrappers -unsigned $__mul_wrapper \
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Y Y_WIDTH \
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-unsigned $__add_wrapper \
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Y Y_WIDTH ;;
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.. literalinclude:: /code_examples/macc/macc_xilinx_test.ys
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:language: yoscrypt
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:start-after: part c
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:end-before: end part c
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.. figure:: /_images/code_examples/macc/macc_xilinx_test1c.*
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:class: width-helper
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@ -208,57 +205,37 @@ Wrapping in ``test2``:
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.. figure:: /_images/code_examples/macc/macc_xilinx_test2b.*
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:class: width-helper
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.. code:: yoscrypt
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techmap -map macc_xilinx_wrap_map.v
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connwrappers -unsigned $__mul_wrapper \
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Y Y_WIDTH \
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-unsigned $__add_wrapper \
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Y Y_WIDTH ;;
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.. literalinclude:: /code_examples/macc/macc_xilinx_test.ys
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:language: yoscrypt
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:start-after: part c
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:end-before: end part c
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.. figure:: /_images/code_examples/macc/macc_xilinx_test2c.*
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:class: width-helper
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Extract in ``test1``:
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.. code:: yoscrypt
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design -push
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read_verilog macc_xilinx_xmap.v
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techmap -map macc_xilinx_swap_map.v
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techmap -map macc_xilinx_wrap_map.v;;
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design -save __macc_xilinx_xmap
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design -pop
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extract -constports -ignore_parameters \
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-map %__macc_xilinx_xmap \
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-swap $__add_wrapper A,B ;;
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.. figure:: /_images/code_examples/macc/macc_xilinx_test1c.*
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:class: width-helper
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.. literalinclude:: /code_examples/macc/macc_xilinx_test.ys
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:language: yoscrypt
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:start-after: part d
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:end-before: end part d
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.. figure:: /_images/code_examples/macc/macc_xilinx_test1d.*
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:class: width-helper
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Extract in ``test2``:
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.. code:: yoscrypt
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design -push
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read_verilog macc_xilinx_xmap.v
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techmap -map macc_xilinx_swap_map.v
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techmap -map macc_xilinx_wrap_map.v;;
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design -save __macc_xilinx_xmap
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design -pop
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extract -constports -ignore_parameters \
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-map %__macc_xilinx_xmap \
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-swap $__add_wrapper A,B ;;
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.. figure:: /_images/code_examples/macc/macc_xilinx_test2c.*
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:class: width-helper
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.. literalinclude:: /code_examples/macc/macc_xilinx_test.ys
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:language: yoscrypt
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:start-after: part d
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:end-before: end part d
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.. figure:: /_images/code_examples/macc/macc_xilinx_test2d.*
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:class: width-helper
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@ -267,13 +244,14 @@ Unwrap in ``test2``:
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.. figure:: /_images/code_examples/macc/macc_xilinx_test2d.*
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:class: width-helper
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.. literalinclude:: /code_examples/macc/macc_xilinx_test.ys
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:language: yoscrypt
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:start-after: part e
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:end-before: end part e
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.. figure:: /_images/code_examples/macc/macc_xilinx_test2e.*
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:class: width-helper
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.. code:: yoscrypt
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techmap -map macc_xilinx_unwrap_map.v ;;
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Symbolic model checking
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-----------------------
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