From 0fb511905a22987d929507e2c58e00c59ed03292 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Thu, 16 Nov 2023 09:46:47 +1300 Subject: [PATCH] docs: more tidying Fix 010 pdf link. Swap yosys script code blocks for literal includes. Fix broken example code. --- .../appendix/APPNOTE_010_Verilog_to_BLIF.rst | 2 +- .../code_examples/macc/macc_xilinx_test.ys | 20 +++-- .../interactive_investigation.rst | 2 +- docs/source/using_yosys/yosys_flows.rst | 88 +++++++------------ 4 files changed, 50 insertions(+), 62 deletions(-) diff --git a/docs/source/appendix/APPNOTE_010_Verilog_to_BLIF.rst b/docs/source/appendix/APPNOTE_010_Verilog_to_BLIF.rst index cc658f03f..ff404cb53 100644 --- a/docs/source/appendix/APPNOTE_010_Verilog_to_BLIF.rst +++ b/docs/source/appendix/APPNOTE_010_Verilog_to_BLIF.rst @@ -29,7 +29,7 @@ Download ======== This document was originally published in April 2015: -:download:`Converting Verilog to BLIF PDF` +:download:`Converting Verilog to BLIF PDF` .. Installation diff --git a/docs/source/code_examples/macc/macc_xilinx_test.ys b/docs/source/code_examples/macc/macc_xilinx_test.ys index 6e91a04ff..47bf399b2 100644 --- a/docs/source/code_examples/macc/macc_xilinx_test.ys +++ b/docs/source/code_examples/macc/macc_xilinx_test.ys @@ -1,24 +1,32 @@ +# ============================================================================ +# part a read_verilog macc_xilinx_test.v read_verilog -lib -icells macc_xilinx_unwrap_map.v read_verilog -lib -icells macc_xilinx_xmap.v hierarchy -check ;; - +# end part a show -prefix macc_xilinx_test1a -format dot -notitle test1 show -prefix macc_xilinx_test2a -format dot -notitle test2 +# ============================================================================ +# part b techmap -map macc_xilinx_swap_map.v;; - +# end part b show -prefix macc_xilinx_test1b -format dot -notitle test1 show -prefix macc_xilinx_test2b -format dot -notitle test2 +# ============================================================================ +# part c techmap -map macc_xilinx_wrap_map.v connwrappers -unsigned $__mul_wrapper Y Y_WIDTH \ -unsigned $__add_wrapper Y Y_WIDTH;; - +# end part c show -prefix macc_xilinx_test1c -format dot -notitle test1 show -prefix macc_xilinx_test2c -format dot -notitle test2 +# ============================================================================ +# part d design -push read_verilog macc_xilinx_xmap.v techmap -map macc_xilinx_swap_map.v @@ -29,12 +37,14 @@ design -pop extract -constports -ignore_parameters \ -map %__macc_xilinx_xmap \ -swap $__add_wrapper A,B ;; - +# end part d show -prefix macc_xilinx_test1d -format dot -notitle test1 show -prefix macc_xilinx_test2d -format dot -notitle test2 +# ============================================================================ +# part e techmap -map macc_xilinx_unwrap_map.v;; - +# end part e show -prefix macc_xilinx_test1e -format dot -notitle test1 show -prefix macc_xilinx_test2e -format dot -notitle test2 diff --git a/docs/source/using_yosys/more_scripting/interactive_investigation.rst b/docs/source/using_yosys/more_scripting/interactive_investigation.rst index fe78c66c5..ad7b9613d 100644 --- a/docs/source/using_yosys/more_scripting/interactive_investigation.rst +++ b/docs/source/using_yosys/more_scripting/interactive_investigation.rst @@ -424,7 +424,7 @@ Yosys script for ASIC synthesis of the Amber ARMv2 CPU. if (ARST) Q <= ARST_VALUE; else - <= D; + Q <= D; endmodule diff --git a/docs/source/using_yosys/yosys_flows.rst b/docs/source/using_yosys/yosys_flows.rst index b73ee59db..170db416c 100644 --- a/docs/source/using_yosys/yosys_flows.rst +++ b/docs/source/using_yosys/yosys_flows.rst @@ -41,15 +41,23 @@ The extract pass .. todo:: add/expand supporting text +.. literalinclude:: /code_examples/macc/macc_simple_test.ys + :language: yoscrypt + :lines: 1-2 + .. figure:: /_images/code_examples/macc/macc_simple_test_00a.* :class: width-helper - before `extract` + before :cmd:ref:`extract` + +.. literalinclude:: /code_examples/macc/macc_simple_test.ys + :language: yoscrypt + :lines: 6 .. figure:: /_images/code_examples/macc/macc_simple_test_00b.* :class: width-helper - after `extract` + after :cmd:ref:`extract` .. literalinclude:: /code_examples/macc/macc_simple_test.v :language: verilog @@ -59,13 +67,6 @@ The extract pass :language: verilog :caption: ``docs/source/code_examples/macc/macc_simple_xmap.v`` -.. code:: yoscrypt - - read_verilog macc_simple_test.v - hierarchy -check -top test - - extract -map macc_simple_xmap.v;; - .. literalinclude:: /code_examples/macc/macc_simple_test_01.v :language: verilog :caption: ``docs/source/code_examples/macc/macc_simple_test_01.v`` @@ -191,14 +192,10 @@ Wrapping in ``test1``: .. figure:: /_images/code_examples/macc/macc_xilinx_test1b.* :class: width-helper -.. code:: yoscrypt - - techmap -map macc_xilinx_wrap_map.v - - connwrappers -unsigned $__mul_wrapper \ - Y Y_WIDTH \ - -unsigned $__add_wrapper \ - Y Y_WIDTH ;; +.. literalinclude:: /code_examples/macc/macc_xilinx_test.ys + :language: yoscrypt + :start-after: part c + :end-before: end part c .. figure:: /_images/code_examples/macc/macc_xilinx_test1c.* :class: width-helper @@ -208,57 +205,37 @@ Wrapping in ``test2``: .. figure:: /_images/code_examples/macc/macc_xilinx_test2b.* :class: width-helper -.. code:: yoscrypt - - techmap -map macc_xilinx_wrap_map.v - - connwrappers -unsigned $__mul_wrapper \ - Y Y_WIDTH \ - -unsigned $__add_wrapper \ - Y Y_WIDTH ;; +.. literalinclude:: /code_examples/macc/macc_xilinx_test.ys + :language: yoscrypt + :start-after: part c + :end-before: end part c .. figure:: /_images/code_examples/macc/macc_xilinx_test2c.* :class: width-helper Extract in ``test1``: -.. code:: yoscrypt - - design -push - read_verilog macc_xilinx_xmap.v - techmap -map macc_xilinx_swap_map.v - techmap -map macc_xilinx_wrap_map.v;; - design -save __macc_xilinx_xmap - design -pop - - extract -constports -ignore_parameters \ - -map %__macc_xilinx_xmap \ - -swap $__add_wrapper A,B ;; - .. figure:: /_images/code_examples/macc/macc_xilinx_test1c.* :class: width-helper +.. literalinclude:: /code_examples/macc/macc_xilinx_test.ys + :language: yoscrypt + :start-after: part d + :end-before: end part d + .. figure:: /_images/code_examples/macc/macc_xilinx_test1d.* :class: width-helper Extract in ``test2``: -.. code:: yoscrypt - - design -push - read_verilog macc_xilinx_xmap.v - techmap -map macc_xilinx_swap_map.v - techmap -map macc_xilinx_wrap_map.v;; - design -save __macc_xilinx_xmap - design -pop - - extract -constports -ignore_parameters \ - -map %__macc_xilinx_xmap \ - -swap $__add_wrapper A,B ;; - .. figure:: /_images/code_examples/macc/macc_xilinx_test2c.* :class: width-helper +.. literalinclude:: /code_examples/macc/macc_xilinx_test.ys + :language: yoscrypt + :start-after: part d + :end-before: end part d + .. figure:: /_images/code_examples/macc/macc_xilinx_test2d.* :class: width-helper @@ -267,13 +244,14 @@ Unwrap in ``test2``: .. figure:: /_images/code_examples/macc/macc_xilinx_test2d.* :class: width-helper +.. literalinclude:: /code_examples/macc/macc_xilinx_test.ys + :language: yoscrypt + :start-after: part e + :end-before: end part e + .. figure:: /_images/code_examples/macc/macc_xilinx_test2e.* :class: width-helper -.. code:: yoscrypt - - techmap -map macc_xilinx_unwrap_map.v ;; - Symbolic model checking -----------------------